Insulated channel field effect transistor with an electric...

Details Insulated channel field effect transistor with an electric... Insulated channel field effect transistor with an electric...

1998-10-02

2004-05-11

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S350000, C257S351000

Reexamination Certificate

active

06734498

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to transistors and more particularly to a field effect transistor have an electric field terminal region.
2. Background Art
Referring to
FIG. 1
, a prior art bulk metal oxide semiconductor field effect transistors (MOSFET)
10
includes a source (S), drain (D), and gate (G). The gate includes a conductive polysilicon (poly) layer which is separated from a channel by a thin silicon dioxide insulator (gate oxide) layer. MOSFET
10
is an n-channel MOSFET (nMOSFET). Typically, the channel between the source and drain is doped with N type material. The source, drain, and doped channel are formed in a p-well, which in turn is formed in a p-substrate, or are formed directly in the p-substrate.
Referring to
FIG. 2
, a prior art silicon on insulator (SOI) n-channel MOSFET
20
(SOI transistor
20
) includes a source (S), drain (D), and gate (G). The gate includes a poly layer, which is separated from the doped channel by a gate oxide layer. A p-well is separated from a p-substrate by an oxide insulator
22
. SOI transistor
20
is referred to as a partially depleted (PD) SOI transistor because oxide insulator
22
is relatively away from the source and drain.
Referring to
FIG. 3
, a prior art SOI n-channel MOSFET
30
includes a source (S), drain (D), and gate (G) (with a poly layer), a gate oxide layer, and a doped channel. In contrast to SOI transistor
20
, an oxide insulator layer
32
is positioned close to the surface of SOI transistor
30
. Insulator layer
32
is adjacent (i.e., very close to or are actually touching) the source and drain. SOI transistor
20
is referred to as a fully depleted (FD) SOI transistor because oxide insulator
22
is adjacent to the source and drain and close to the channel. The junction capacitance (Cj) of the source and drain are reduced by positioning insulator oxide layer
22
close to the source and drain, so there is little or no pn junction.
Delta-doped MOSFETs include a doping region under and close to the channel, as shown in C. Wann et al., “A Comparative Study of Advanced MOSFET Concepts,” IEEE Transactions on Electron Devices, Vol. 43, No. 10, October 1996, pp. 1742-1753. As shown in C. Wann et al., p. 1743, the doping region is touching the source and drain. The channel can become contaminated with the doping from the doping region.
Each of these transistors suffers from short channel effects (SCE). One cause of SCE in transistors
10
,
20
, and
30
is that electric field lines between the source and the substrate and between the drain and the substrate are spread throughout much of the channel reducing the effective electrical length (Leff) of the channel.
FIG. 3
illustrates an example of an electric field line E between the source and substrate. One cause of SCE in Delta-doped transistors are dopants in the channel. Accordingly, there is a need for a transistor with improved SCE.
SUMMARY
In one embodiment, the invention includes a field effect transistor having a substrate, a source, and a drain. An electric field terminal region is in the substrate. A body is above the electric field terminal region between the source and drain. There is a barrier between the electric field terminal region and the body.
In another embodiment, the invention includes a field effect transistor having an insulator layer and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate is above the body and between the source and drain. An electric field terminal region is included in the substrate.


REFERENCES:
patent: 4907053 (1990-03-01), Ohmi
patent: 5294821 (1994-03-01), Iwamatsu
patent: 5359219 (1994-10-01), Hwang
patent: 5461250 (1995-10-01), Burghartz et al.
patent: 5621239 (1997-04-01), Horie et al.
patent: 5807772 (1998-09-01), Takemura
patent: 5889302 (1999-03-01), Liu
patent: 5981345 (1999-11-01), Ryum et al.
patent: 6054734 (2000-04-01), Aozasa et al.
International PCT Search Report dated Jan. 11, 2000 for application no. PCT/US99/21540 (3 pages).
C. Wann et al., “A Comparative Study of Advanced MOSFET Concepts,” IEEE Transactions on Electron Devices, vol. 43, No. 10, Oct. 1996, pp. 1742-1753.

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