Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-11
2004-09-07
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000
Reexamination Certificate
active
06787447
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming integrated circuitry, and in particular, to dual damascene processing methods, and resultant integrated circuitry constructions.
BACKGROUND OF THE INVENTION
Interconnection techniques are used in semiconductor processing to electrically interconnect devices over a semiconductor wafer. Historically, the semiconductor industry has used subtractive etch or lift off techniques as a primary metal-patterning technique. Subtractive techniques typically involve depositing a metal layer over a wafer and subsequently masking and etching metal material from over undesired portions of the wafer. Escalating density, performance, and manufacturing requirements associated with semiconductor wiring have led to changes in interconnection technology. To meet these needs, a technology called dual damascene has been developed. See for example, Kaanta,
Damascene: A ULSI Wiring Technology
, VMIC Conference, Jun. 11-12, 1991, page 144-152; Licata,
Dual Damascene AL Wiring
for 256M DRAM, VMIC Conference, Jun. 27-29, 1995, pages 596-602; U.S. Pat. Nos. 5,595,937, 5,598,027, 5,635,432, and 5,612,254.
This invention arose out of concerns associated with providing improved semiconductor processing methods and structures. In particular, the invention arose out of concerns associated with providing improved processing methods and structures which utilize and comprise dual damascene interconnection technology.
SUMMARY OF THE INVENTION
Semiconductor processing methods of forming integrated circuitry, and in particular, methods of forming such circuitry utilizing dual damascene technology, and resultant integrated circuitry constructions are described. In one embodiment, a substrate is provided having a circuit device. At least three layers are formed over the substrate and through which electrical connection is to be made with the circuit device. The three layers comprise first and second layers having an etch stop layer interposed therebetween. A contact opening is formed through the three layers and a patterned masking layer is formed over the three layers to define a conductive line pattern. Material of an uppermost of the first and second layers is selectively removed relative to the etch stop layer and defines a trough joined with the contact opening. Conductive material is subsequently formed within the trough and contact opening. In another embodiment, a contact opening is formed through a plurality of layers and has an aspect ratio of no less than about 10:1. A trench is defined in an uppermost layer of the plurality of layers proximate the contact opening. Conductive material is formed within the contact opening and at least a portion of the trench, with the conductive material being in electrical communication.
REFERENCES:
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5518963 (1996-05-01), Park
patent: 5595937 (1997-01-01), Mikagi
patent: 5598027 (1997-01-01), Matsuura
patent: 5612254 (1997-03-01), Mu et al.
patent: 5635423 (1997-06-01), Huang et al.
patent: 5635432 (1997-06-01), Honda et al.
patent: 5702982 (1997-12-01), Lee et al.
patent: 5726100 (1998-03-01), Givens
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5891799 (1999-04-01), Tsui
patent: 5980657 (1999-11-01), Farrar et al.
patent: 5989997 (1999-11-01), Lin et al.
patent: 6042999 (2000-03-01), Lin et al.
patent: 6054768 (2000-04-01), Givens et al.
patent: 6057227 (2000-05-01), Harvey
patent: 6057231 (2000-05-01), Givens et al.
patent: 6057239 (2000-05-01), Wang et al.
patent: 6060386 (2000-05-01), Givens
patent: 6080655 (2000-06-01), Givens et al.
patent: 6091148 (2000-07-01), Givens et al.
patent: 6200895 (2001-03-01), Givens et al.
patent: 6271593 (2001-08-01), Givens et al.
patent: 6297156 (2001-10-01), Farrar et al.
patent: 6316356 (2001-11-01), Farrar et al.
patent: 6319813 (2001-11-01), Givens
patent: 6461963 (2002-10-01), Givens et al.
patent: 6482735 (2002-11-01), Givens et al.
patent: 6534408 (2003-03-01), Givens et al.
patent: 2002/0006719 (2002-01-01), Farrar et al.
patent: 2002/0033498 (2002-03-01), Farrar et al.
patent: 2003/0045093 (2003-03-01), Givens et al.
Carter et al., “Dual Damascene: A USLI Wiring Technology”, Jun. 11-12, 1991, pp. 144-152, VMIC Conference, 1991 IEEE.
T. Licata et al., “Dual Damascene AI Wiring For 256M Dram”, Jun. 27-29, 1995, pp. 596-602, VMIC Conference, 1995 ISMIC—104/95/0596.
H.J. Barth, “Integration Aspects Of A Hi-Fill Barrier With A High Pressure Aluminum Contact Fill”, Jun. 27-29, 1995, pp. 52-58, VMIC Conference, 1195 ISMIC—104/95/0052.
C. Dobson et al., A 3-Level 0.35um interconnection process using an innovative high pressure aluminium plug technology, pp. 31-37, Jun. 27-29, 1995, VMIC Conference, 1995 ISMIC—104/95/0031.
Fourson George
Micro)n Technology, Inc.
Toledo Fernando
Wells St. John P.S.
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