Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-06-28
2004-01-27
Fahmy, Wael (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S595000, C438S736000, C438S738000
Reexamination Certificate
active
06682996
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for patterning a semiconductor feature.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
At various stages in the fabrication of semiconductor devices, it may be necessary to pattern one or more layers to form a semiconductor feature, such as a gate structure or an interconnect, for example. In an embodiment in which a semiconductor feature is conductive, contacts may be fabricated to contact the semiconductor feature. In addition or alternatively, portions of the semiconductor feature may need to be insulated from contacts or other conductive structures, which are not intended for contact with the semiconductor feature. For example, an upper surface of a gate structure may need to be insulated from an overlying interconnect line such that shorting the gate may be prevented. Such an insulation configuration may be particularly useful in an embodiment in which the interconnect line is connected to a contact structure formed self-aligned to the gate structure. As such, in some embodiments, forming a semiconductor feature may include etching a conductive layer along with a dielectric layer arranged above or below the conductive layer. In addition or alternatively, some conductive features include multiple conductive layers. Furthermore, some conductive features include barrier layers interposed between multiple conductive layers and/or dielectric layers to prevent the diffusion of dopants to underlying or overlying layers.
In any embodiment, such an inclusion of additional layers may increase the aspect ratio of semiconductor features. An aspect ratio as used herein generally describes the ratio between the height and width of a semiconductor feature when viewed in cross section. Furthermore, as the device densities of semiconductor devices are continually being increased, profile and dimension requirements of semiconductor device features must be further optimized. For example, the lateral dimensions of semiconductor features are continually being reduced in order to increase the device density on a semiconductor substrate. Generally, however, the height of semiconductor features may not be reduced in proportion to the lateral dimensions. In this manner, the aspect ratio of semiconductor features in advanced semiconductor devices may be higher than semiconductor devices with a low density of features.
In general, conventional photolithography and etch processes used to pattern a semiconductor feature may be limited in their abilities to form features with high aspect ratios. In particular, the lateral widths of semiconductor features may be limited by the image resolution of photolithography equipment used to pattern the semiconductor feature. Such image resolution is typically dependent on the wavelength of the photolithographic tool. For example, the minimum resolvable feature size of a 193 nm photolithographic tool may be approximately 0.1 microns. As such, in order to obtain a structure with a feature size with a dimension smaller than approximately 0.1 microns, a smaller wavelength tool may need to be used.
However, there are disadvantages with using smaller wavelength photolithographic tools. For example, photolithographic tools are typically expensive and therefore, purchasing new photolithographic tools for each new development of devices with reduced feature sizes may be cost prohibitive. Furthermore, smaller wavelength photolithographic tools used to produce such devices may require substantial process development to produce such small feature sizes. In addition, the materials used for photoresist films and underlying anti-reflective coating (ARC) layers may be dependent on the wavelength used with the photolithographic tool and therefore, may need to be revised for consistency with the new photolithographic tools. In some cases, problems, such as poor image resolution, poor etch selectivity, or patterning clarity such as line edge roughness, may arise with such immature technologies and chemistries. As a result, the installation of new photolithographic equipment and its associated chemistry may delay the development of devices with reduced feature sizes.
In addition, the thickness of resist layers and ARC layers which are able to be patterned by photolithography equipment is generally reduced as the lateral dimension resolvable by the photolithography equipment is reduced. For example, in some embodiments, the maximum thickness of a resist layer may be approximately 3000 angstroms and the maximum thickness of an ARC layer may be approximately 900 angstroms when using a 193 nm photolithographic tool. As such, in some embodiments, the height of the semiconductor feature may be reduced during the formation of the feature since the mask layer (i.e., the resist layer and ARC layer combined) will be removed prior to the completion of the etch process.
Such a reduction in height may reduce the thickness of one or more layers within the semiconductor feature beyond its design specification. As a result, the height reduction of the semiconductor feature may alter the functionality of a subsequently formed semiconductor device, rendering the device defective or non-functional. For example, the thickness of the conductive portions of a semiconductor feature may be reduced by such a formation process. Such a reduction in thickness of a conductive portion may undesirably increase the resistance of the semiconductor feature, thereby degrading the functionality of the device. Additionally or alternatively, the dielectric portions of a semiconductor feature may be reduced. In such an embodiment, the reduction in dielectric thickness may not allow adequate insulation of the conductive portions of the semiconductor device. Consequently, a reduction in dielectric thickness may undesirably allow a conductive feature to short to the conductive portions of the semiconductor feature.
It would therefore be desirable to develop a method for fabricating a semiconductor feature such that portions of the semiconductor feature are not reduced beyond their design specifications. In particular, it may be desirable to develop a method for patterning a semiconductor feature with relatively large aspect ratios.
SUMMARY OF THE INVENTION
The problems outlined above may be in large part addressed by a method for processing a semiconductor topography. In particular, the method may include patterning a plurality of layers spaced below a sacrificial hardmask layer. In some embodiments, the method may include depositing the sacrificial hardmask layer above a lower hardmask layer arranged above a stack of layers prior to patterning the stack of layers. Accordingly, in some embodiments, the method may minimize the removal of the lower hardmask layer during the patterning process of the stack of layers. In some cases, the patterning process may include removing the entire sacrificial hardmask layer. In particular, the method may include patterning an upper portion of the stack of layers using the sacrificial hardmask layer as a first mask and patterning a lower portion of the stack of layers using the lower hardmask layer as a second mask. In other embodiments, patterning the lower portion of the plurality of layers may include removing the sacrificial hardmask layer. In yet other embodiments, patterning the upper and lower portions of the plurality of layers may both include removing portions of the sacrificial hardmask layer. Consequently, a semiconductor topography is provided herein which includes a first hardmask layer arranged upon and in contact with a plurality of layers and a sacrificial hardmask layer arranged upon and in contact with the first hardmask layer. Such a sacrificial hardmask layer may include substantially different etch characteristics than one or more upper layers of the plurality of layers and substantially similar etch
Conley & Rose, P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Fahmy Wael
Smoot Stephen W.
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