Method of fabricating a wiring on a planarized surface

Details Method of fabricating a wiring on a planarized surface Method of fabricating a wiring on a planarized surface

1997-12-02

1999-08-17

Bowers, Charles

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

438781, 438623, 438624, 438631, 438632, 438699, 438760, H01L 214763

Patent

active

059407344

ABSTRACT:
An insulating film 16, made of BPSG, etc., is formed on a substrate 10 by CVD, covering an uneven surface, and then is subjected to thermal treatment to fluidize the film and to reduce the step. Hydrogen silsesquioxane resin solution is coated on the film 16 by spin coating, subjected to the first annealing at a relatively low temperature, and then to the second annealing at relatively high temperature, to form a glass film 18. The lamination of the films 16 and 18 is etched back under the dry etching conditions where the etch rates of the films 16 and 18 become approximately equal, until film 18 is completely removed, to planarize the film 16. A wiring is formed on the planarized surface. The surface of the insulating film serving as an underlying layer of a wiring can be planarized uniformly and with good reproducibility.

REFERENCES:
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patent: 5506177 (1996-04-01), Kishimoto et al.
patent: 5518962 (1996-05-01), Murao
patent: 5552346 (1996-09-01), Huang et al.
patent: 5607880 (1997-03-01), Suzuki et al.
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2, p. 232, 1990.

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