Methods of forming transistors

Details Methods of forming transistors Methods of forming transistors

2002-02-07

2004-07-06

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S153000, C438S596000

Reexamination Certificate

active

06759285

ABSTRACT:

TECHNICAL FIELD
This invention relates to electrical interconnection and thin film transistor fabrication methods, and to integrated circuitry having electrically interconnected layers.
BACKGROUND OF THE INVENTION
The invention grew out of needs associated with thin film transistors (TFTs) and their usage in high-density static random access memories (SRAMs). A static memory cell is characterized by operation in one of two mutually exclusive and cell-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a “high” voltage to indicate a “set” operating state. The memory cell output produces a “low” voltage to indicate a “reset” memory cell operating state. A low or reset output voltage usually represents a binary value of zero, and a high or set output voltage represents a binary value of one.
A static memory cell is said to be bi-stable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.
The operation of a static memory cell is in contrast to other types of memory cells, such as dynamic cells, which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods. A dynamic memory cell has no feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, effectively resulting in loss of data.
Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along a different path than has the design of dynamic memories.
Ongoing efforts in SRAM circuitry to improve active loads has brought about the development of TFTs in attempts to provide low leakage current as well as high noise immunity. While the invention grew out of needs associated with TFTs of SRAM circuitry, the artisan will appreciate applicability of the invention to other types of circuitry.
Some recent TFT technology employs fully surrounded field effect transistor (PET) gate regions, such as shown in FIG.
1
. Such illustrates a semiconductor wafer fragment
10
comprised of a bulk substrate
12
and overlying insulating layer
14
. Bulk substrate
12
includes an n+ active area
16
which electrically connects with a gate of a thin film transistor, which is generally indicated by numeral
18
. Such transistor includes a channel region
20
. The adjacent source and drain of such transistor would be into and out of the plane of the paper on which
FIG. 1
appears. A first or bottom gate conductive layer
22
is provided over insulating layer
14
and extends to electrically connect with active area
16
. A bottom gate oxide dielectric layer
24
is provided atop bottom gate layer
22
and contacts with the bottom of transistor channel region
20
. A top gate layer
26
overlies bottom dielectric layer
24
and the top of transistor channel region
20
. An electrically conductive top is gate layer
28
is provided and patterned over top gate oxide dielectric layer
26
. A contact opening
30
is provided through top and bottom gate oxide layers
26
,
24
respectively, over active area
16
prior to top gate layer
28
deposition. Such results in electrical interconnection of top gate
28
with a bottom gate
22
. Thus, channel region
20
is surrounded by conductive gate material for switching transistor
18
“on”.
The above described construction requires photolithography and etch steps for producing contact opening
30
, and separate patterning of top gate electrode
23
. It would be desirable to provide methods of forming thin film transistors which minimize photolithography and etching steps.


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