Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-03-11
2004-07-20
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S317000, C257S321000, C257S335000, C257S345000
Reexamination Certificate
active
06765260
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory (NVM) and the methods for fabricating and for operating the same. More particularly, the present invention relates to a flash memory with a self-aligned spilt gate and methods for fabricating and operating the same.
2. Background of the Invention
Flash memory can retain information even when power is interrupted and is small in size, faster in reading/programming and can resist vibration, so it is widely used. A flash memory comprises a floating gate and a control gate that are isolated by a dielectric layer, wherein the floating gate is isolated from the substrate by a tunnel oxide layer. During the writing/erase operation, electrons are injected into/ejected from the floating gate with a voltage applied to the control gate. During the reading operation, a working voltage is applied to the control gate. At this time, the charging state on the floating gate causes a conducting status of ON or OFF of the channel that is under the floating gate. The conducting state of ON/Off corresponds to the data of 0/1.
The data in the above mentioned flash memory is erased by increasing the potential of the substrate, the drain/source or the control gate relative to the floating gate. The electrons ejected from the floating gate flow into the substrate or the drain/source via the tunnel oxide layer by tunneling. This mechanism is known as substrate erase mechanism or drain/source side erase mechanism. Another mechanism is to eject the electrons in the floating gate to the control gate via the dielectric layer. However, the amount of the electrons ejected from the floating gate is difficult to precisely control during erasing. If too many electrons are ejected from the floating gate, the floating gate has net positive charges. This phenomenon is called “over-erasing”. When the over-erasing effect is severe, the channel under the floating gate is switched on even when the working voltage is not applied to the control gate. This may lead to an error in data reading. Therefore, a split gate design is adopted in many kinds of flash memory. One of the characteristics of the split gate is that the control gate has a portion above the floating gate and another portion above the substrate with separation of a gate dielectric layer. Thus when the over-erasing occurs to switch on the channel under the floating gate even if there is no working voltage applied, the channel under the control gate remains closed. Therefore, the drain and the source still cannot be electrically connected. This prevents the data from being erratically determined.
The process for fabricating the split gate flash memory in the prior art is described as following with reference to
FIG. 1A
to
1
D.
As shown in
FIG. 1A
, a substrate
100
is provided. A gated oxide
104
, a polysilicon layer
106
and a dielectric layer
108
is sequentially formed on the substrate
100
, wherein the polysilicon layer
106
serves as a floating gate. A thermal oxidation process is carried out to form an oxide layer
110
on the sidewalls of the polysilicon layer
106
and on the substrate
100
.
As shown in
FIG. 1B
, a conformal polysilicon layer
112
is formed on the substrate
200
covering the dielectric layer
108
and oxide layer
110
.
As shown in
FIG. 1C
, a photolithography process and an etching process are performed to form control gates
112
a
and
112
b
covering a portion of floating gate
106
and a portion of the substrate
100
. An ion implantation process is carried out to form a common source
116
in the substrate
100
between the control gates
112
a
and
112
b
and a drain
114
in the substrate
100
on the other side of the floating gate
106
.
There are some problems in the conventional method for fabricating the spilt gate flash memory. One is that the control gates
112
a
and
112
b
have non-uniform width as shown in FIG.
1
D. Since the patterning process is not carried out by using a self-aligned method, the misalignment of the photolithography process will lead to asymmetric control gates
112
a
and
112
b
. Therefore, the size of the control gate, the channel length and the channel current of each memory are also not constant. This affects the quality of the product. The other problem is that the process window in the conventional method is small since a self-aligned method is not used. This causes a disadvantage that the cell dimension is hard to scale down. Another problem is that two adjacent memory cells are unsymmetrical and have different electric properties since the memory cells are not formed on strip-like active regions.
SUMMARY OF INVENTION
The present invention provides a flash memory with a self-aligned spilt gate and the methods for fabricating and for operating the same to solve the problem that the adjacent memory cells are unsymmetrical and not potential equivalent as in the prior art.
The present invention also provides a method for operating a flash memory with a self-aligned spilt gate in order to reduce the operating voltage in the programming, erasing or reading operation.
The present invention provides a flash memory with a self-aligned spilt gate. The flash cell consists of a substrate, a deep n-type well and a shallow p-type well, a gate oxide layer, a control gate, a capping layer, a floating gate, a tunnel oxide layer, a drain, a common source and a pocket p-well. The deep n-type well is located in the substrate and the shallow p-type well is located in the deep n-well. The control gate is located on the substrate covering a portion of the shallow p-type well. The gate oxide is located between the control gate and the substrate and the capping layer is located on the control gate. The floating gate is located on one sidewall of the control gate and the capping layer and over the substrate. The tunnel oxide layer is located between the control gate and the floating gate and between the floating gate and the substrate. In the present invention, a dielectric spacer is further on the other sidewall of the control gate and the capping layer to protect the control gate from being damaged during a subsequent metal interconnection process. The drain is located in the deep n-type well under the dielectric spacer and adjacent to the control gate. A common source is located in and connected to the deep n-type well and under extending to a portion of the floating gate and adjacent to the shallow p-type well. A pocket p-well is located in the substrate around the drain and electrically connecting the divided shallow p-type wells beside the drain to make the shallow p-type well of each cell potential equivalent.
The present invention provides a method for fabricating a flash memory with a self-aligned spilt gate. An isolation is formed on a substrate to define an active region. A deep n-type well is formed in a substrate and a shallow p-type well is formed in the deep n-well. A gate oxide layer, a control gate and a capping layer are formed on a portion of the shallow p-type well. A tunnel oxide layer is formed on the sidewalls of the control gate and on the substrate by conducting a thermal process. A conformal conductive layer is formed covering the capping layer and the substrate. The conformal conductive layer is etched back to form a conductive spacer on the sidewalls of the capping layer and the control gate. Thereafter, the conductive spacer on one side of the control gate is removed to leave the conductive spacer on the other side as a floating gate. A common source is formed in and connects to the deep n-well, wherein the common source under extends to a portion of the floating gate about a half of the floating gate width. A drain is formed in the shallow p-type well adjacent to the control gate. A dielectric spacer is formed on the sidewall of the control gate without the conductive spacer formed thereon to protect the control gate from being damaged in subsequent etching processes. A pocket p-well is formed around the drain to connect with the shallow p-type well beside the dr
Hsu Cheng-Yuan
Hung Chih-Wei
Jiang Chyun IP Office
Powerchip Semiconductor Corp.
Tran Minhloan
Tran Tan
LandOfFree
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