Non-volatile semiconductor memory device having shared row...

Details Non-volatile semiconductor memory device having shared row... Non-volatile semiconductor memory device having shared row...

2002-08-15

2004-05-04

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

26, 26, 26, 26, 26, 26, 26

Reexamination Certificate

active

06731540

ABSTRACT:

FIELD OF THE INVENTION
This disclosure generally relates to a non-volatile memory device and, more particularly, to a row selection circuit for applying wordline voltages based on each operation mode to wordlines of a selected block.
BACKGROUND OF THE INVENTION
There are growing demands for electrically erasable and programmable semiconductor memory devices in a semiconductor memory device. In addition, such memory devices trend toward higher capacity and integration density. A NAND flash memory device is an example of a non-volatile memory device that can meet higher capacity and integration density without the need to refresh stored data. Since the NAND flash memory device continuously holds data even when a power supply is interrupted, it has widely been used in electronic apparatuses (e.g., portable terminals, handheld computers, cellular phones, digital cameras, etc.).
A conventional NAND flash memory device
10
is illustrated in FIG.
1
.
Referring to
FIG. 1
, a NAND flash memory device includes a memory cell array
20
, a row selection circuit (X-SEL)
40
, and a sense and latch circuit
60
. The memory cell array
20
has a plurality of cell strings (or NAND strings)
21
that are coupled to bitlines BL
0
-BLm, respectively. The cell string
21
of each column includes a string selection transistor SST serving as a first selection transistor, a ground selection transistor GST serving as a second selection transistor, and a plurality of EEPROM cells MCn (n=0-15) serially connected between the selection transistors SST and GST. The string selection transistor SST of each column has a drain coupled to a corresponding bitline and a gate coupled to a string selection line SSL. The ground selection transistor GST has a source coupled to a common source line CSL and a gate coupled to a ground selection line GSL. Flash EEPROM cells MC
15
-MC
0
are serially connected between a source of the string selection transistor SST and a drain of the ground selection transistor GST. Further, the flash EEPROM cells MC
15
-MC
0
are each coupled to their corresponding wordlines WL
15
-WL
0
.
A memory cell array
20
constitutes a memory block and is a so-called “mat”. Although only one memory block is illustrated in the figure, a number of memory blocks may be arranged with the same structure as shown in FIG.
1
. In this case, the memory blocks are to share bitlines BL
0
-BLm.
The string selection line SSL, the wordlines WL
0
-WL
15
, and the ground selection line GSL are electrically connected to a row selection circuit
40
. The row selection circuit
40
selects one of the wordlines WL
0
-WL
15
according to address information, and applies wordline voltages based on each operation mode to a selected wordline and unselected wordlines. This will be explained in detail below. Bitlines BL
0
-BLm arranged through the memory cell array
20
are electrically connected to the sense & latch circuit
60
. The sense and latch circuit
60
senses data from flash EEPROM cells of a selected wordline through the bitlines BL
0
-BLm in a read operation mode, and applies a power supply voltage or a ground voltage to the bitlines BL
0
-BLm based on data to be programmed in a program operation mode, respectively.
In a program operation mode, the row selection circuit
40
applies a program voltage Vpgm (e.g., 18V) to a selected wordline and applies a pass voltage Vpass (e.g., 10V) to unselected bitlines. In a read operation mode, the row selection circuit
40
applies a ground voltage GND to a selected wordline and applies a read voltage Vread (e.g., 4.5V) to unselected wordlines. A program voltage, a pass voltage, and a read voltage are higher than a power supply voltage (e.g., 3V). In order to apply a voltage higher than a power supply voltage according to address information, a circuit capable of switching the higher voltage is necessary for the row selection circuit
40
. A switch pump scheme or a boosting scheme is used to construct the circuit capable of switching the higher voltage.
A row selection circuit
40
using the switch pump scheme is partially illustrated in FIG.
2
.
Referring to
FIG. 2
, a row selection circuit
40
includes a decoding block
42
, a switch pump block
44
, and a switch block
46
. The decoding block
42
has NAND gates G
1
and G
2
. Address signals DA
1
-DAi are supplied to the NAND gate G
1
, and an output signal and a control signal BLKWLdis are supplied to the NAND gate G
2
. The control signal BLKWLdis is held high during an erase/program/read operation. The switch pump block
44
is coupled to a BLKWL node (or referred to as “block wordline”), and has a NAND gate G
3
, a capacitor C
1
, and NMOS transistors MN
1
-MN
4
that are connected as shown in the figure. The switch block
46
has pass (or transfer) transistors SW
1
-SW
0
each transferring selection signals SS, S
15
-S
0
, and GS to their corresponding signal lines SSL, WL
15
-WL
0
, and GSL. Gates of the pass transistors SW
0
-SW
17
are commonly coupled to the BLKWL node. The decoding block
42
and the switch pump block
44
constitute a block decoder for selecting a memory block.
When at least one of the address signals DA
1
-DAi is low, an output signal of the decoding block
42
is made low. In this case, the switch pump block
44
does not perform a pump operation irrespective of a clock signal CLK. On the other hand, when all the address signals DA
1
-DAi are high, the output signal of the decoding block
42
is made high. In this case, the switch pump block
44
operates based on a low-to-high/high-to-low transition of the clock signal CLK (wherein the low level is a ground voltage level, and the high level is a power supply voltage level). According to the transition of the clock signal CLK, a capacitor C
1
repeatedly carries out a charge/discharge operation. If the capacitor C
1
is charged by a pumping charge according to the high-to-low transition of the clock signal CLK, the pumping charge is transferred through an NMOS transistor MN
1
to increase a voltage of the BLKWL node. When the clock signal CLK then transitions from low to high, a VPP
0
voltage (Vread in a read operation, and Vpgm in a program operation) is applied to a gate of the NMOS transistor MN
1
through an NMOS transistor MN
2
that is shut off by a gate-source voltage difference after predetermined time.
If the capacitor C
1
is recharged according to the high-to-low transition of the clock signal CLK, the pumping charge is transferred through the MNOS transistor MN
1
to increase a voltage of the BLKWL node. When the clock signal then transition from low to high, the VPP
0
voltage is applied to the gate of the NMOS transistor MN
1
via the NMOS transistor MN
2
. As the above procedure is repeated, the voltage of the BLKWL node may be boosted up to “VPP
0
+Vtn
3
” finally (wherein the “Vtn
3
” represents a threshold voltage of an NMOS transistor MN
3
, and serves to clamp the voltage of the BLKWL node when it is boosted over a required voltage). Therefore, the BLKWL node has a high voltage enough to transfer the program voltage Vpgm/read voltage Vread to a corresponding wordline.
However, a switch pump structure shown in
FIG. 2
is not suitable for a low voltage NAND flash memory device. This reason is described below. The clock signal CLK is made low as a power supply voltage is lowered, which means that pumping time required for boosting the voltage of the BLKWL node up to a required voltage becomes elongated. Further, as the pumping operation is carried out, threshold voltages of the NMOS transistors MN
1
and MN
2
are increased by the body effect. As a result, a voltage level of the BLKWL node is limited by the increased threshold voltage. A row selection circuit using a boosting scheme has been proposed for overcoming disadvantages of the pumping structure.
A circuit diagram of a row selection circuit using a boosting scheme is illustrated in FIG.
3
.
Referring to
FIG. 3
, a row selection circuit
40
includes a decoding block
42
′, a precharge block
44
′, a switch block
46
′,

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