Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2003-09-05
2004-07-20
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S203000, C365S230010, C365S230080, C365S189080, C365S185230
Reexamination Certificate
active
06765832
ABSTRACT:
TITLE OF THE INVENTION
Semiconductor Memory Device with Word Line Shift Configuration
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device executing redundancy repair using a so-called word line shift configuration.
2. Description of the Background Art
As a general defect repair measure in a semiconductor memory device, a word line redundancy configuration has been known in which a defective memory cell is repaired on the basis of a memory cell row as a unit by controlling selection of a spare word line provided correspondingly to spare memory cells arranged so as to form a spare row, and a word line provided correspondingly to a normal cell row.
Especially, in such a word line redundancy configuration, a word line shift configuration has been known in which a so-called shift redundancy is applied. In a configuration disclosed in FIG. 1 of Japanese Patent Laying-Open No. 2002-15592, for example, each of word line select circuits 11 provided correspondingly to respective word lines drives a corresponding word line into a selected state or a non-selected state according to a voltage at an output node 32. A shift switch 38 capable of connecting to output node 32 of another word line select circuit 11 is provided in the interior of each of word line select circuits 11, thereby realizing a word shift configuration in which a defective word line is replaced with an adjacent word line and, also, the subsequent word lines are sequentially shifted to use a spare word line.
Generally, in the word line redundancy configuration, a spare row is arranged in the outermost end of a memory cell array. Therefore, in the case where a defective row is directly replaced with a spare row, a difference in access time between a replacement of the defective row and each of the other memory cell rows become larger. On the other hand, in the word line shift configuration in which a defective word line is replaced with an adjacent word line, a difference in access time when the defective row is selected can be reduced.
Further, in the word line shift configuration in which a shift redundancy scheme is adopted, shift states of a spare word line and word lines can be predetermined according to a location of a defective row; therefore, no need arises for a redundancy decoder, leading to an advantage in that no necessity occurs for executing a redundancy determination in each access. As a result, a memory access at a high speed is realized in the shift redundancy configuration as compared with the case where the redundancy decoder is employed without adopting the shift redundancy configuration.
On the other hand, when an unintentional variation occurs in voltage at an output node controlling selection
on-selection of a corresponding word line (e.g. an output node
32
in
FIG. 1
of the above publication) regardless of a redundancy configuration in a word line select circuit, an unexpected word line is selected, resulting in simultaneous selection of a plurality of word lines in error, that is “multi-word line selection.” When the multi-word line selection occurs, neither data reading nor data writing is normally executed.
In the above word line shift configuration, however, in each word line select circuit, unavoidable increase arises in the number of electric paths connected to the above output node due to arrangement of shift switches. Hence, with the word line shift configuration adopted, a risk of multi-word line selection is enhanced
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device with a word line shift configuration having less of a risk of word line multi-selection.
A semiconductor memory device according to one aspect of the present invention includes: a memory cell array including a plurality of memory cells arranged in rows and columns and a plurality of spare memory cells arranged so as to form first and second spare rows in respective regions adjacent to the plurality of memory cells; a plurality of word lines provided correspondingly to respective rows of the plurality of memory cells; first and second spare word lines provided correspondingly to the first and second spare rows, respectively; a plurality of word line drivers provided correspondingly to the respective plurality of word lines to each control a voltage on a corresponding one of the plurality of word lines; and first and second spare word line drivers provided correspondingly to the first and second spare word lines, respectively, to control voltages on the first and second spare word lines, wherein the plurality of word line drivers and the first and second spare word line drivers are sequentially disposed in accordance with arrangement of the plurality of word lines and the first and second spare word lines in the memory cell array, each of the plurality of word line drivers and the first and second spare word line drivers includes: an output node; a drive circuit driving a corresponding one of the plurality of word lines and the first and second spare word lines into one of a selected state and a non-selected state according to a voltage at the output node; and a precharge switch precharging the output node to a first voltage prior to a row select operation and, also, disconnecting the output node from the first voltage in the row select operation, each of the plurality of word line drivers further includes: a decode unit connecting a first internal node to a second voltage in the row select operation according to a result of row selection; a control switch provided between a second internal node and the first internal node to connect both to each other in the row select operation and, also, disconnect both from each other prior to the row select operation; a first shift switch connected between one output node adjacent to the output node of a corresponding one of the plurality of word line drivers on a first side along a direction of arrangement of the plurality of word line drivers and the first and second spare word line drivers, and the second internal node of the corresponding word line driver; a second shift switch connected between the output node of the corresponding word line driver, and the second internal node of the corresponding word line driver; and a third shift switch connected between one output node adjacent to the output node of the corresponding word line driver on a second side opposite to the first side, and the second internal node of the corresponding word line driver, and the semiconductor memory device further includes a shift control circuit controlling turning-on and -off of the first to third shift switches in each of the plurality of word line drivers in the row selection operation on the basis of an address of a defective memory cell row.
A semiconductor memory device according to another aspect of the present invention includes: a memory cell array including a plurality of memory cells arranged in rows and columns and a plurality of spare memory cells arranged so as to form J spare rows (where J is a natural number); a plurality of word lines provided correspondingly to respective rows of the plurality of memory cells; J spare word lines provided correspondingly to the respective J spare rows; a plurality of word line drivers provided correspondingly to the respective plurality of word lines to each control a voltage on a corresponding one of the plurality of word lines; and J spare word line drivers provided correspondingly to the respective J spare word lines to each control a voltage on a corresponding one of the spare word lines, wherein the plurality of word line drivers and the J spare word line drivers are sequentially arranged in accordance with arrangement of the plurality of word lines and the J spare word lines in the memory cell array, each of the plurality of word line drivers and the J spare word line drivers includes: an output node; a drive circuit driving a corresponding word line or a spare word line
McDermott Will & Emery LLP
Renesas Technology Corp.
Yoha Connie C.
LandOfFree
Semiconductor memory device with word line shift configuration does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device with word line shift configuration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with word line shift configuration will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3249686