Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-07
2004-09-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257S350000, C438S149000, C438S153000, C438S154000, C438S479000, C438S517000
Reexamination Certificate
active
06787855
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of semiconductor device and a method of manufacturing the same, and more particularly to a structure of a MOSFET that can reduce the scale of elements, increase the operation speed, and reduce the electric power consumption, and a method of manufacturing the same.
2. Description of the Background Art
FIG. 27
is a top view illustrating a structure of a general MOSFET. A channel region (not appearing in
FIG. 27
) is formed under a gate electrode
101
, and a pair of source/drain regions
102
are formed to sandwich the channel region. Further, contact plugs
103
for connecting the source/drain regions
102
to source/drain wirings (not illustrated) are formed.
In such a MOSFET, the area of the source/drain regions
102
tend to be reduced in order to reduce the scale of elements.
FIG. 28
is a top view illustrating a structure of a conventional MOSFET with reduced area of the source/drain regions. Source/drain regions
104
are formed instead of the source/drain regions
102
shown in FIG.
27
. While the width of the source/drain regions in the channel length direction is L102 in the MOSFET shown in
FIG. 27
, the width is L104 (<L102) in the MOSFET shown in
FIG. 28
, whereby the reduction of the area of the source/drain regions is achieved.
FIG. 29
is a cross-sectional view illustrating a cross section structure with respect to the position along the line X
100
shown in FIG.
28
. An SOI substrate
105
has a multilayered structure in which a silicon substrate
106
, a BOX (buried oxide) layer
107
, and a silicon layer
108
are layered in this order. An element isolation dielectric film
109
such as STI (shallow trench isolation) is selectively formed in a top surface of the silicon layer
108
.
In an element formation region of the SOI substrate
105
defined by the element isolation dielectric film
109
, source/drain regions
104
forming a pair to sandwich a p-type body region
110
(corresponding to the aforesaid channel region) are formed in the top surface of the silicon layer
108
. The source/drain regions
104
have an n
+
-type impurity diffusion region
111
formed from the top surface of the silicon layer
108
to reach the top surface of the BOX layer
107
, and a silicide layer
112
formed by turning the top surface of the silicon layer
108
into silicide.
On the body region
110
, a gate structure is formed having a multilayered structure in which a gate oxide film
113
and a gate electrode
101
are layered in this order. A side wall
120
made of silicon oxide is formed on the side surface of the gate structure. The gate electrode
101
has a polysilicon layer
114
formed on the gate oxide film
113
and a silicide layer
115
formed on the polysilicon layer
114
.
Further, an interlayer dielectric film
118
made of silicon oxide is formed to cover the respective exposed surfaces of the silicide layers
115
,
112
, the side wall
120
, and the element isolation dielectric film
109
. Source/drain wirings
119
made of aluminum or the like are formed on the interlayer dielectric film
118
. Further, contact plugs
103
for connecting the source/drain wirings
119
to the source/drain regions
104
are selectively formed in the interlayer dielectric film
118
. The contact plugs
103
each have a contact hole
116
formed from the top surface of the interlayer dielectric film
118
to reach the top surface of the silicide layer
112
, and a conductor plug
117
that fills the inside of the contact hole
116
.
According to such a conventional MOSFET, scale reduction of elements can be achieved by reducing the area of the source/drain regions
104
. Further, in a MOSFET using an ordinary bulk substrate instead of an SOI substrate, by reducing the area of the source/drain regions, the junction area between the source/drain regions and the silicon substrate having different conductivity types from each other is reduced, thereby leading to reduction of the source/drain capacitance.
However, in accordance with the reduction of the area of the source/drain regions
104
, the distance between the contact plugs
103
and the gate electrode
101
becomes smaller, so that parasitic capacitance
121
generated between the two increases, thereby raising a problem.
SUMMARY OF THE INVENTION
A semiconductor device according to the first aspect of the present invention includes: an SOI substrate having a semiconductor substrate, a dielectric layer, and a semiconductor layer formed in this order; a transistor having a drain region and a source region respectively formed in the semiconductor layer, and a gate electrode formed via a gate dielectric film on a channel region sandwiched between the drain region and the source region; an interlayer dielectric film formed on the transistor; a drain wiring and a source wiring formed on the interlayer dielectric film; a first conductor formed in the interlayer dielectric film for connecting the drain wiring to the drain region; and a second conductor formed in the interlayer dielectric film for connecting the source wiring to the source region, wherein the drain region has a first part being adjacent to the channel region and a second part formed to protrude from the first part so that a part of outer peripheries of the drain region extends away from the gate electrode in a plan view, and the first conductor is connected to the second part of the drain region.
According to the first aspect of the present invention, the distance between the first conductor and the gate electrode can be increased as compared with a semiconductor device in which the first conductor is connected to the first part of the drain region. Therefore, the parasitic capacitance generated between the first conductor and the gate electrode can be reduced.
Moreover, since the SOI substrate is adopted, the drain region can be formed from the top surface of the semiconductor layer to reach the top surface of the dielectric layer. Therefore, although the area of the drain region increases by the area of the formed second part, the increase of the drain capacitance accompanying the increase of the area can be restrained to the minimum.
A semiconductor device according to the second aspect of the present invention is the semiconductor device according to the first aspect, wherein the first part of the drain region has a width of 0.2 to 0.5 &mgr;m with respect to a channel length direction of the channel region, and the second part of the drain region has a length of 0.1 to 0.5 &mgr;m with respect to a direction protruding from the first part of the drain region.
A semiconductor device according to the third aspect of the present invention is the semiconductor device according to the first aspect, wherein the first part of the drain region has a plurality of corner parts in a plan view, and the second part of the drain region is formed to protrude obliquely with respect to a channel width direction of the channel region from the corner part which is not adjacent to the gate electrode.
According to the third aspect of the present invention, the distance between the first conductor and the gate electrode can be increased as compared with a semiconductor device in which the second part of the drain region is formed to protrude in the channel width direction. Therefore, the parasitic capacitance generated between the two can be reduced.
A semiconductor device according to the fourth aspect of the present invention is the semiconductor device according to the first aspect, wherein a bottom surface of the first conductor is partially in contact with the second part of the drain region by being shifted away from the gate electrode.
According to the fourth aspect of the present invention, the distance between the first conductor and the gate electrode can be further increased. Therefore, the parasitic capacitance generated between the two can be further reduced.
A semiconductor device according to the fifth aspect of the present invention is the semiconductor d
Hirano Yuuichi
Maeda Shigenobu
Maegawa Shigeto
Flynn Nathan J.
Mandala Jr. Victor A.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
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