Semiconductor integrated circuit system

Details Semiconductor integrated circuit system Semiconductor integrated circuit system

2001-10-30

2004-03-30

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S409000, C257S491000, C361S056000

Reexamination Certificate

active

06713817

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-333580, filed Oct. 31, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit system including a plurality of semiconductor devices, which are required to have properties substantially the same as each other in operation and, more particularly, to a system, which solves a problem caused by fluctuations in the properties of the semiconductor devices due to the electrical effects of plasma when a plasma process is performed for manufacturing the system. When an integrated circuit system including transistors of the MIS(Metal-Insulator-Semiconductor) type, which is represented by the MOS (Metal-Oxide-Semiconductor) type, is manufactured, the properties of transistors are affected by electrical charge stresses appearing in the wiring layers due to a plasma process. In this respect, for example, Jpn. Pat. Appln. KOKAI Publication No. 8-97416, “Semiconductor Device”, (Prior Art 1) explains as follows:
2. Description of the Related Art
When a layer is subjected to patterning by plasma etching in a manufacturing process, particles electrically charged by plasma are accumulated on the patterned layer. Accordingly, the patterned layer, such as a metal wiring layer of aluminum, comes into a charged-up state. Where the wiring layer is connected through a contact hole to the gate electrode of a transistor, made of poly-crystalline silicon or the like, electrical charges on the charged-up wiring layer flow into the gate electrode. As a result, a surge voltage is applied to a gate insulating film, e.g., an oxide film, between the gate electrode and a channel region therebelow. It follows that the gate insulating film suffers a stress, by which the gate insulating film is degraded or broken down. This phenomenon depends on a ratio of the surface area of the wiring layer charged with electricity during plasma etching, relative to the surface area of the gate insulating film; which is called “antenna ratio”.
In the first stage of degradation or breakdown of a gate insulating film, which is caused by a surge stress brought about the plasma electrical charges, the gate insulating film comes to easily trap hot carriers, thereby increasing the threshold voltage of the transistor. In the second stage of degradation or breakdown of a gate insulating film, a leakage current flows between the gate electrode and the substrate or the source/drain regions.
The Prior Art 1 discloses that plasma damage, such as fluctuation in Vth (threshold voltage), decrease in gm (trans-conductance), gate leakage current, and gate breakdown, is caused, depending on the plasma processing time, antenna ratio (the ratio of a wiring surface area (circumferential length) relative to a gate surface area (circumferential length)), and so forth. The Prior Art 1 also discloses a countermeasure for preventing variation in plasma damage to a gate insulating film due to the antenna ratio.
FIG. 11
is a circuit diagram showing this conventional countermeasure. As shown in
FIG. 11
, the wiring that connects a preceding internal circuit
202
to the gate electrode of a MOS transistor
204
in a logic circuit is provide with diode elements
206
and resistor elements
208
.
Jpn. Pat. Appln. KOKAI Publication No. 6-61440, “Integrated Circuit Device, Data Processing Method In Integrated Circuit Device, And Data Processing Device Of Integrated Circuit Device”, (Prior Art 2), discloses another countermeasure for preventing variation in plasma damage to a gate insulating film due to the antenna ratio.
FIG. 12
is a circuit diagram showing this conventional countermeasure. As shown in
FIG. 12
, the gate electrodes of two MOS transistors
214
a
and
214
b
disposed in an inverter cell
212
are connected to diode elements
218
disposed in a protection circuit cell
216
.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit system comprising:
a semiconductor substrate;
first and second semiconductor devices formed on the substrate and required to have properties substantially the same as each other in operation, the first and second semiconductor devices respectively including first and second channel regions arranged in a surface of the substrate, and first and second gate electrodes disposed on the first and second channel regions via gate insulating films;
first and second wiring layers connected to the first and second the gate electrodes, respectively; and
a relaxing structure configured to relax fluctuation in the properties of the first and second semiconductor devices, the fluctuation being caused by electrical effects of plasma when a plasma process is performed for manufacturing the system,
wherein the relaxing structure comprises first and second short-circuiting elements respectively connected to the first and second wiring layers and substantially equivalent to each other, the first and second short-circuiting elements being configured to short-circuit the first and second gate electrodes with the first and second channel regions, respectively, when the first and second wiring layers are supplied with electrical potentials beyond operation ranges of electrical potentials, which are applied to the first and second gate electrodes in the operation of the first and second semiconductor devices, respectively.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit system comprising:
a semiconductor substrate;
first and second semiconductor devices formed on the substrate and required to have properties substantially the same as each other in operation, the first and second semiconductor devices respectively including first and second channel regions arranged in a surface of the substrate, and first and second gate electrodes disposed on the first and second channel regions via gate insulating films;
first and second wiring layers connected to the first and second the gate electrodes, respectively; and
a relaxing structure configured to reduce fluctuations in the properties of the first and second semiconductor devices, the fluctuations being caused by electrical effects of plasma when a plasma process is performed for manufacturing the system,
wherein the relaxing structure comprises metal wiring layers forming the first and second wiring layers, derived from a metal film at a lowest level and disposed on the substrate via an insulating film, the second wiring layer is shorter than the first wiring layer, and is connected to a dummy wiring layer derived from the metal film at the lowest level, and the dummy wiring layer is sized such that the first and second gate electrodes are affected by the electrical effects of plasma to substantially the same extent as each other when a plasma process is performed for manufacturing the system.


REFERENCES:
patent: 5760445 (1998-06-01), Diaz
patent: 5998299 (1999-12-01), Krishnan
patent: 6091114 (2000-07-01), Mogul et al.
patent: 6600176 (2003-07-01), Noguchi
patent: 2002/0000579 (2002-01-01), Aoyama
patent: 2002/0094625 (2002-07-01), Hashimoto et al.
patent: 6-61440 (1994-03-01), None
patent: 8-97416 (1996-04-01), None
patent: 9-283638 (1997-10-01), None
patent: 11-186502 (1999-07-01), None
Wolf, Stanley, “Silicon Processing for the VLSI Era, vol. 2: Process Integration,” p. 443, (1990).
Decision of Rejection mailed on Jun. 26, 2003 corresponding to Taiwanese Patent Application No. 090125755 filed on Oct. 18, 2001.

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