Low temperature process for fabricating layered superlattice mat

Details Low temperature process for fabricating layered superlattice mat Low temperature process for fabricating layered superlattice mat

1995-03-21

1996-04-16

Breneman, R. Bruce

Fishing, trapping, and vermin destroying

117 90, 437133, H01L 2915

Patent

active

055082262

ABSTRACT:
A liquid precursor containing a metal is applied to a first electrode, RTP baked at a temperature of 700.degree. C., and annealed at the same temperature for from 3 to 5 hours to form a layered superlattice material. A second electrode is formed to form a capacitor, and a second anneal is performed at a temperature of 700.degree. C. If the material is strontium bismuth tantalate, the precursor contains u mole-equivalents of strontium, v mole-equivalents of bismuth, and w mole-equivalents of tantalum, where 0.8.ltoreq.u.ltoreq.1.0, 2.0 v.ltoreq.2.3, and 1.9.ltoreq.w.ltoreq.2.1.

REFERENCES:
patent: 5046043 (1991-09-01), Miller et al.
patent: 5423285 (1995-06-01), Paz de Araujo et al.
patent: 5434102 (1995-07-01), Watanabe et al.
patent: 5439845 (1995-08-01), Watanabe et al.

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