Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-10-08
2004-07-20
Thai, Xuan M. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06766406
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to integrated circuits and, more specifically, to a field programmable universal serial bus application specific integrated circuit and a method of operation thereof.
BACKGROUND OF THE INVENTION
Today many computer systems, such as personal computers, include Universal Serial Bus (USB) technology. USB is a Plug-and-Play and Hot-Plugable interface for connecting a computer system to external devices, such as printers, scanners, keyboards, mice, telephones, and digital cameras. Plug-and-Play refers to the ability of a computer system to automatically configure and install the software drivers needed to communicate with the device plugged into the USB interface. Accordingly, with plug and play, there is no need to configure switches, jumpers, or other elements. HotPlugable refers to the ability to add and remove devices to the USB while the computer system is running and have the operating system automatically recognize the change. USB is expected to replace serial and parallel ports and become the preferred means of connecting low and medium bandwidth peripherals.
Typically, a USB supports data transfer rates of up to 12 Mbps (12 million bits per second) and a single USB port can accommodate up to 127 devices, such as mice, modems and keyboards. USB devices typically consist of peripheral function logic, a USB logical device, and the USB interface. A variety of different USB interfaces exist which would prove useful for a number of applications. However, design flexibility problems limit the implementation of USB interfaces.
Two main devices employed within USB interfaces are Field Programmable Gate Array (FPGA) chips and Application-Specific Integrated Circuits (ASIC) chips, each having its own benefits and limitations. FPGAs provide a great degree of flexibility when employed within a USB interface. Analogous with their name, FPGAs are field programmable devices that employ programmable gates to allow various configurations and can be reprogrammed in the field. This provides the ability to determine and correct any errors which may not have been detectable prior to use. Additionally, the FPGAs may be reprogrammed to accommodate new devices connected thereto.
One of the most noticeable drawbacks of an FPGA, however, is unfavorable performance. While FPGAs may be reprogrammed if a performance issue or an error is detected, this is not always the best solution to the problem. For example, depending on certain factors, an integrated device that may not be reprogrammed may be desired over a device that may be reprogrammed. One such factor may be the latency tolerable in the circuit. Also, compared to other interfaces, FPGAs experience certain density and speed limitation issues. The speed limitation may be attributed to the re-programmable nature of the FPGA's gates.
As previously stated, ASIC chips are also commonly used and implemented as part of USB interfaces. Compared to FPGAs, ASIC chips are regarded in the industry as being very fast and providing a high performance guarantee. However, ASIC chips also experience certain limitations. One of the main limitations of ASIC chips, and probably the most notable deterrent to using them more frequently, is their inability to be reprogrammed. Because they cannot be reprogrammed, an extremely large amount of time and money must be provided upon inception of design and manufacture.
One of the most common concerns for digital designers for ASIC products is achieving optimum design flexibility without sacrificing performance. In order to support multiple interfaces or increased functionality, designers are typically forced to instantiate almost every conceivable functionality or interface at the expense of the product size and cost. Otherwise, the potential functionality or interface flexibility of the production product will be sacrificed.
Accordingly, what is needed in the art is a USB interface device that includes the benefits of prior art FPGAs and ASIC chips, however, a USB interface device that does not experience their drawbacks.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a field programmable universal serial bus application specific integrated circuit and a method of operation thereof. In one embodiment, the field programmable universal serial bus application specific integrated circuit includes: (1) a universal serial bus function core configured to transmit and receive data via a universal serial bus and (2) a programmable logic core having an array of dynamically configurable arithmetic logic units. The programmable logic core is configured to interface with the universal serial bus function core and implement at least one application level function capable of performing protocol conversion to at least one processor bus protocol.
In another embodiment, the present invention provides a method of operating a field programmable universal serial bus application specific integrated circuit that includes: (1) configuring a programmable logic core, having an array of dynamically configurable arithmetic logic units, to interface with a universal serial bus function core and implement at least one application level function capable of performing protocol conversion to at least one processor bus protocol, (2) transmitting and receiving data via a universal serial bus with the universal serial bus function core.
The present invention also provides, in one advantageous embodiment, a universal serial bus protocol adapter system that includes a field programmable universal serial bus application specific integrated circuit having: (1) a universal serial bus function core that transmits and receives data via a universal serial bus, and (2) a programmable logic core having an array of dynamically configurable arithmetic logic units. The programmable logic core interfaces with the universal serial bus function core and implements at least one application level function capable of performing protocol conversion to at least one processor bus protocol. The universal serial bus protocol adapter system further includes a host processor that receives and transmits data with the field programmable universal serial bus application specific integrated circuit in the at least one processor bus protocol, and at least one universal serial bus transceiver, coupled to the field programmable universal serial bus application specific integrated circuit, that provides a physical interface to at least one peripheral device coupled to the universal serial bus.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 6044428 (2000-03-01), Rayabhari
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Neil Hastie et al. “The Implementation of Hardware Subroutines on Field Programmable Gate Arrays” IEEE, 1990, pp. 31.4.31.4.4.*
Paul Dillen, Adaptive Hardware Becomes a Reality using Electrically Reconfigurable Arrays (ERAs), GEC Plessey Semiconductors, 1990. pp. 2/1-2/10.
Gasperini Peter
Singh Rajiv K.
Hitt Gaines PC
LSI Logic Corporation
Thai Xuan M.
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