Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2002-10-30
2004-07-27
Deb, Anjan K. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
C324S699000, C324S696000
Reexamination Certificate
active
06768323
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to interconnect technology in integrated circuit fabrication, and more particularly, to a system and method for electrically determining the location of an extrusion site along a length of an interconnect.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, common components of a monolithic IC (integrated circuit) include interconnect structures such as a first metal line
102
and a second metal line
104
.
FIG. 2
shows a cross-sectional view of the first and second metal lines
102
and
104
along line I—I of
FIG. 1
formed to be surrounded by dielectric material
106
on a semiconductor substrate
108
. Interconnect structures are formed to electrically connect integrated circuit devices formed on the semiconductor substrate
108
as known to one of ordinary skill in the art of integrated circuit fabrication.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As IC dimensions are scaled down, the width of the metal lines
102
and
104
are scaled down, and the distance between the metal lines
102
and
104
is decreased as the density of the locations of the interconnect structures is increased for connecting the IC devices having scaled down dimensions. Referring to
FIG. 3
, as the width of the metal lines
102
and
104
is scaled down, the current density through the metal lines
102
and
104
is increased. With higher current density, the metal lines
102
and
104
exhibit a higher rate of electromigration failure from flux divergence, as known to one of ordinary skill in the art of integrated circuit fabrication. For example, an extrusion
110
of metal material from the first metal line
102
may reach the second metal line
104
to undesirably short-circuit the two metal lines
102
and
104
.
Occurrence of such an extrusion
110
is even more probable in current interconnect technology where the metal lines
102
and
104
are comprised of copper surrounded by material
106
that is a low-K dielectric (i.e., a dielectric material having a dielectric constant lower than that of silicon dioxide S
102
). The low-K dielectric material
106
is advantageous for lower capacitance between the interconnect structures as the distance between the metal lines
102
and
104
is decreased. Such lower capacitance results in higher speed performance of the integrated circuit and also in lower power dissipation.
In addition, such lower capacitance results in lower cross-talk between the interconnect structures. Lower cross-talk between interconnect structures is especially advantageous when the interconnect structures are disposed closer together as device density continually increases. However, the dielectric material
106
with low-K typically is softer (i.e., has lower density) and may even be porous. Thus, the undesired extrusion
110
is especially more likely to occur with such low-K dielectric material
106
.
In addition, as device dimensions are further scaled down, a diffusion barrier layer material is formed to be thinner when surrounding interconnect having scaled down dimensions for minimizing resistance of the interconnect. However, a thinner diffusion barrier layer material surrounding the interconnect results in a higher probability of the occurrence of an extrusion from such interconnect.
During characterization of an integrated circuit fabrication process, the location of the extrusion
110
along the length of any of the metal lines
102
or
104
is desired to be determined. Referring to
FIGS. 4 and 5
, in the prior art, when the extrusion
110
is disposed below the top surface of the surrounding dielectric material
106
, the top surface of the materials on the semiconductor substrate
108
is polished down until the extrusion
110
is exposed. Then, the polished top surface is inspected using microscopy tools to visually locate the extrusion
110
.
Such a prior art technique for locating the extrusion
110
is disadvantageous because the top surface of the materials on the semiconductor substrate
108
may not be polished down enough (as illustrated in
FIG. 6
) or may be polished down too much (as illustrated in FIG.
7
). In those cases, the extrusion
110
would not be detected visually. In addition, it is difficult to polish down the proper amount of material until the extrusion is exposed to be detected visually since the location of the extrusion is not known a priori. Furthermore, visually determining the location of the extrusion
110
by scanning the entire top surface of materials on the semiconductor substrate
106
using microscopy tools is tedious and time-consuming.
Nevertheless, during characterization of an integrated circuit fabrication process, the location of the extrusion
110
along the length of any of the metal lines
102
or
104
is desired to be determined. Thus, a mechanism is desired for determining the location of an extrusion along the length of a metal line in an easy and accurate manner.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a system and method determines the location of an extrusion site along a length of an interconnect electrically in an easy and accurate manner.
In one embodiment of the present invention, in a system and method for determining a location of an extrusion site along a length of an interconnect having a width (w
i
), a resistivity (&rgr;
i
), and a height (h
i
), an extrusion monitor structure having a width (w
m
), a resistivity (&rgr;
m
), and a height (h
m
), surrounds the sides of the interconnect along the length of the interconnect. The width (w
m
) of the extrusion monitor structure is larger than the width (w
i
) of the interconnect. The interconnect and the surrounding extrusion monitor structure are separated by a dielectric material. A first via is coupled to the interconnect at a first via location, and a second via is coupled to the extrusion monitor structure at a second via location. The first via and the second via are separated by a via distance (L
v
), and the extrusion site is located along the length of the interconnect at an extrusion site distance (L
extrusion
) from the first via and between the first via and the second via. An extrusion of the interconnect at the extrusion site short-circuits the interconnect to the extrusion monitor structure. A resistance meter is coupled between the first via and the second via for measuring a resistance (R
total
) between the first via and the second via. The extrusion site distance (L
extrusion
) is then determined from the following relationship:
R
total
=(&rgr;
i
/h
i
)*(
L
extrusion
/w
i
)+(&rgr;
m
/h
m
)*((
L
v
−L
extrusion
)/
w
m
).
In another embodiment of the invention, the interconnect and the extrusion monitor structure are comprised of a same material such that the resistivity (&rgr;
i
) of the interconnect is substantially same as the resistivity (&rgr;
m
) of the extrusion monitor structure. In addition, the height (h
i
) of the interconnect is substantially same as the height (h
m
) of the extrusion monitor structure. In that case, the extrusion site distance (L
extrusion
) is determined as follows:
L
extrusion
=(
w
i
/(
w
m
−w
i
))*(R
total
*h
i
w
m
/&rgr;
i
−L
v
).
In this manner, the location of the extrusion site along the length of the interconnect is determined electrically by measuring the resistance between the first via and the second via for an easy and accurate technique of determining the location of the extrusion site. Thus, the time-consuming hit-or-miss technique of polishing down to the extrusion site for locating the extrusion visually in the prior art is avoided.
These and other fe
Hau-Riege Christine
Hau-Riege Stefan
Advanced Micro Devices , Inc.
Choi Monica H.
Deb Anjan K.
LandOfFree
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