Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-18
2004-03-23
Whitmore, Stacy A (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06711728
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a function synthesizing method for converting a program that is written in a general-purpose programming language (e.g., the C language) into a logic circuit that performs an operation defined by the program, and to a function synthesizing apparatus that executes the above function synthesizing method. The invention also relates to a recording medium on which a program of the above function synthesizing method is recorded.
2. Description of Conventional Technology
In electronic circuit designing, converting a program that is written in a general-purpose programming language (e.g., the C language) into a logic circuit that performs an operation defined by the program (hereinafter referred to as “function synthesis”) is commonly done.
Data indicating a post-conversion logic circuit is RT (register transfer) level data or gate level data. The RT level data is data written in a hardware description language and defining a logic circuit. The gate level data is data as a combination of transistor gates.
FIG. 21
is a block diagram showing an example configuration of an electronic circuit data (mask data) generation system to which a conventional function synthesizing method is applied.
Specifically, the electronic circuit data generation system shown in
FIG. 21
is a computer apparatus consisting of a CPU (Central Processing Unit) and peripheral circuits and devices. This computer apparatus performs the following operation based on a control program that is recorded in a built-in semiconductor memory (ROM, RAM, or the like) or an external storage device (hard disk, magneto-optical disc, or the like).
In
FIG. 21
, a C program storage section
1
stores a C program that defines an (or a part of) operation of a desired electronic circuit.
A function synthesizing section
102
converts the C program stored in the C program storage section
1
into RT level data (i.e., performs function synthesis).
An optimizing section
3
optimizes the RT level data generated by the function synthesizing section
102
. This optimization is attained by commonizing operation elements (described later).
An RT level data storage section
4
stores the RT level data that has been optimized by the optimizing section
3
.
A logic synthesizing section
5
generates gate level data from the RT level data stored in the RT level data storage section
4
. A Gate level data storage section
6
stores the Gate level data generated by the logic synthesizing section
5
.
A layout section
7
converts the Gate level data stored in the Gate level data storage section
6
into mask data (that is necessary to generate a combination of transistor gates that is indicated by the Gate level data).
A mask data storage section
8
stores the master data generated by the layout section
7
.
After the master data is generated by the above processing, a prescribed manufacturing process (not shown) manufactures a desired electronic circuit by using the master data.
Next, the configuration and operation of the function synthesizing section (i.e., the function synthesizing section
102
in
FIG. 21
) that executes the conventional function synthesizing method will be described.
FIG. 22
is a block diagram showing a configuration example of the function synthesizing section
102
.
FIG. 23
is a flowchart showing an operation example of the function synthesizing section
102
.
As shown in
FIG. 22
, the function synthesizing section
102
is configured by a scheduling section
1021
, an FSM generation section
1022
, a data path generation section
1023
, a combining section
1024
, and a scheduling result storage section
1025
.
With this configuration, when an operator gives the function synthesizing section
102
a function synthesis execution command by using a prescribed operation panel (not shown), the process of the function synthesizing section
102
goes to step S
101
in FIG.
23
.
In step S
101
, the scheduling section
1021
reads out a C program from the C program storage section
1
.
As an example (hereinafter referred to as “conventional example”), assume here that a C program shown in
FIG. 4
is read out.
Then, the scheduling section
1021
disregards output sentences in the read-out C program and generates a data flow graph based on only operation sentences.
The term “output sentence” means a program sentence, such as a print sentence, that is intended for data printing (rather than operation).
In the conventional example, the scheduling section
1021
generates a data flow graph shown in
FIG. 5
based on the C program shown in FIG.
4
.
Then, the process of the function synthesizing section
102
goes to step S
102
in FIG.
23
.
In step S
102
, the scheduling section
1021
divides, by using a prescribed operation clock signal, the data flow graph into operations that are performed at respective clocks of the operation clock signal.
In the conventional example, the scheduling section
1021
divides the data flow graph of
FIG. 5
in a manner shown in FIG.
6
.
The divisional pattern (i.e., the number of operations to be performed at respective clocks) depends on various parameters (relating to electronic circuit designing) that are preset by an operator.
That is, if the parameters are so set as to generate a high-speed electronic circuit, the data flow graph is divided so that as many operations as possible are performed per clock.
On the other hand, if the parameters are so set as to reduce the electronic circuit scale, the data flow graph is divided so that each gate can be reused by as many operations as possible (i.e., operations of the same kind are performed at as many different clocks as possible).
Then, the scheduling section
1021
assigns state names (identification names unique to respective clocks) to respective clocks.
In the conventional example, state names ST
01
, ST
02
, and ST
03
are assigned as shown in FIG.
6
.
In the following, a data flow graph after assigning of state names will be referred to as “state-assigned data flow graph.”
The scheduling section
1021
stores a state-assigned data flow graph in the scheduling result storage section
1025
.
Then, the process of the function synthesizing section
102
goes to step S
104
in FIG.
23
.
In step S
104
, the FSM generation section
1022
generates an FSM (finite state machine) based on the scheduling result (i.e., the state-assigned data flow graph) stored in the scheduling result storage section
1025
.
In the conventional example, the FSM generation section
1022
generates an FSM shown in
FIG. 8
based on the data flow graph shown in FIG.
6
.
As shown in
FIG. 8
, lines extended from the respective states (ST
01
, ST
02
, ST
03
) of the FSM are referred to here as “control signal lines.”
Then, the process of the function synthesizing section
102
goes to step S
106
in FIG.
23
.
In step S
106
, the data path generation section
1023
generates data paths based on the scheduling result (i.e., the state-assigned data flow graph) that is stored in the scheduling result storage section
1025
.
Further, the data path generation section
1023
detects variables that should hold a value over a plurality of states based on the state-assigned data flow graph, and adds flip-flops to signal lines (in the data paths) corresponding to the detected variables.
A trigger signal (control signal) to be applied to each flip-flop is made a signal corresponding to a state that is one-step before a state where the operation is executed by using a value of the variable corresponding to the flip-flop.
In the conventional example, the data path generation section
1023
generates data paths shown in
FIG. 10
based on the data flow graph shown in FIG.
6
.
Since values of variables a and b are used in addition in state ST
02
as shown in
FIG. 6
, in
FIG. 10
a control signal corresponding to state ST
01
is given to the flip-flops corresponding to variables a and b.
Since values of variables c and d are used in addition in state ST
03
, a control signal corresponding
Foley & Lardner
NEC Electronics Corporation
Whitmore Stacy A
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