Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-23
2004-03-23
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S303000
Reexamination Certificate
active
06710389
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, a dynamic random access memory (i.e., DRAM) whose memory cell portion has a trench-type stacked cell structure. More specifically, the present invention relates to a semiconductor memory device including a storage capacity element portion that is suitable for a highly integrated device and has high reliability, and to a method for manufacturing the semiconductor memory device.
2. Description of the Related Art
With the implementation of a smaller-scale device and a larger-capacity DRAM in recent years, the surface area occupied by a single memory cell on a chip of a semiconductor memory device is reduced increasingly.
FIG. 11
is a plan view schematically showing the layout of trench-type stacked cell capacitors (i.e., concave-type capacitors) formed in a memory cell region. In
FIG. 11
, reference numeral
110
denotes a cell plate electrode, Ls
1
denotes the short side length of a cell capacitor, Ls
2
denotes the long side length of the cell capacitor, and Ts
1
denotes the distance between the adjacent cell capacitors.
FIG. 12
is a cross-sectional view taken along the line I-II in FIG.
11
.
FIG. 12
illustrates a cell capacitor A (with a capacitance of C
s1
), a cell capacitor B (with a capacitance of C
s2
) and a cell capacitor C (with a capacitance of C
s3
), which are adjacent to one another. Each of the cell capacitors is a trench-type stacked cell, i.e., the cell capacitor region is recessed, and the plate electrode
110
is exposed on the entire surface. Here, H represents the height of the cell capacitor. These cell capacitors are connected to transfer transistors so as to form a storage capacity element portion (i.e., a DRAM circuit), as shown in FIG.
13
. In
FIG. 13
, WL
1
, WL
2
and WL
3
are word lines, and C
p
is a parasitic capacitance formed between the cell capacitors. The parasitic capacitance C
p
will be described later.
The following is an explanation of the structure shown in FIG.
12
. An interlayer insulating film
111
is deposited on the region where memory cells are formed. The interlayer insulating film
111
has holes for providing storage nodes (i.e., lower electrodes of the memory cells), and conductive films
108
a
,
108
b
and
108
c
that act as the storage nodes are formed in the holes. Each of the storage nodes is connected to a plug
112
via a barrier metal (not shown). A capacitor insulating film
109
and the plate electrode
110
are deposited on the entire surface, including the insides of the holes where the storage nodes have been formed, without removing the interlayer insulating film
111
. In other words, the trench-type stacked cell structure is a cell structure that utilizes only the inner surfaces of the trenches defined by the interlayer insulating film
111
as capacitors.
FIG. 14
is a cross-sectional view showing the structure of conventional simple-stacked memory cells. In
FIG. 14
, capacitor insulating films
102
, and thereon a plate electrode
103
are formed so as to cover cylindrical storage nodes
101
.
FIG. 15
is a cross-sectional view showing the structure of conventional cylindrical cell capacitors. In
FIG. 15
, capacitor insulating films
105
, and thereon a plate electrode
106
are formed so as to cover the inner and outer surfaces of cylindrical storage nodes
104
.
FIGS. 16A
to
16
E are cross-sectional views showing the manufacturing steps of conventional cylindrical cell capacitors. First, as shown in
FIG. 16A
, transfer gate MOS transistors
1603
are formed on a semiconductor substrate (not shown), on which a first interlayer insulating film
1601
is deposited, and then contact plugs
1602
are formed. Next, as shown in
FIG. 16B
, a second interlayer insulating film
1604
is deposited. After deposition of a resist, a hole pattern for storage nodes is formed by photolithography. Using the hole pattern as a mask, holes
1605
for storage nodes are formed in the second interlayer insulating film
1604
by anisotropic dry etching, as shown in FIG.
16
C. After formation of the contact holes, a film for forming storage nodes, e.g., a silicon film is deposited. The silicon film on the second interlayer insulating film
1604
is removed selectively by dry etching or the like, so that the silicon films having a cylindrical shape are left only in the holes
1605
, which serves as cylindrical storage nodes
1606
. Then, the second interlayer insulating film
1604
is removed selectively, e.g., by wet etching, thus leaving the cylindrical storage nodes
1606
on the first interlayer insulating film
1601
, as shown in FIG.
16
D. Finally, as shown in
FIG. 16E
, capacitor insulating films
1607
are formed, followed by a plate electrode
1608
, resulting in memory cell capacitors.
For the structures shown in
FIGS. 14
,
15
and
16
E, the adjacent cell capacitors are connected electrically by the plate electrodes
103
,
106
and
1608
, respectively, each of which has the same electric potential. Therefore, a large parasitic capacitance is not generated between the adjacent cell capacitors even if the plate electrode is covered with an interlayer insulating film (not shown).
FIGS. 17A
to
17
E are cross-sectional views showing the manufacturing steps of the conventional trench-type stacked cell structure described above. The flow of the steps shown in
FIGS. 17A
,
17
B and
17
C is the same as that in
FIGS. 16A
,
16
B and
16
C, i.e., the steps of forming transfer gate MOS transistors
1703
, depositing a first interlayer insulating film
1701
, forming contact plugs
1702
, depositing a second interlayer insulating film
1704
, and forming holes
1705
for storage nodes in the second interlayer insulating film
1704
by lithography and dry etching. After these steps, cylindrical storage nodes
1706
are formed, as shown in FIG.
17
D. Then, a capacitor insulating film
1707
, and thereon a plate electrode
1708
are formed without removing the second interlayer insulating film
1704
, as shown in FIG.
17
E.
The above method for manufacturing the trench-type stacked cell structure eliminates the step of removing the second interlayer insulating film
1704
around the storage nodes and can proceed to the next step. Therefore, the manufacturing steps can be shortened and nonuniformity in the pattern of the cylindrical storage nodes
1706
can be suppressed as well. Moreover, unlike the structures shown in
FIGS. 14 and 15
, it is not necessary to estimate a margin between cell capacitors when the cell capacitor pattern is formed by lithography and dry etching. Thus, this method is very effective in scaling down the device. A large-capacity DRAM can be achieved by arranging a number of small trench-type stacked cells that are produced in such a simple process as described above.
In view of this, the trench-type stacked cell structures shown in
FIGS. 12 and 17E
are expected to be used as the capacitor structure of memory cells in a future DRAM.
In the trench-type stacked cell structure, though the storage nodes (i.e., the lower electrodes) of the individual cell capacitors are separated electrically and have different potentials, an interlayer insulating film is interposed between the adjacent cell capacitors. Therefore, the trench-type stacked cell structure may cause a problem that a larger parasitic capacitance is generated easily compared with other cell capacitor structures, even if the distance between adjacent cell capacitors in the trench-type stacked cell structure is the same as that in the other structures.
For instance, in the example shown in
FIG. 12
, the interlayer insulating films
111
are interposed between the storage node
108
a
of the cell capacitor A and the storage node
108
b
of the cell capacitor B and between the storage node
108
b
and the storage node
108
c
of the cell capacitor C. Thus, a parasitic capacitance C
p4
is generated between each of the cell capacitors so as to make a connection between them, as indicated by the br
Matsushita Electric - Industrial Co., Ltd.
Pham Hoai
Pham Long
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