Fast controlled output buffer

Details Fast controlled output buffer Fast controlled output buffer

2002-12-18

2004-05-11

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S033000, C326S083000

Reexamination Certificate

active

06734701

ABSTRACT:

PRIORITY
This application claims the benefit of priority to Italian patent application number T02002A000811, filed on Sep. 18, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to output buffers, and particularly to controlling an internal VDDQ reference voltage around a target value when short capacitor charge times are desired.
2. Discussion of the Related Art
In integrated devices, an internal power source may be viewed as an RLC model (resistance-inductance-capacitance) between an external pin and integrated transistors. A schematic representation of a simplified circuit according to this model is illustrated at FIG.
1
.
FIG. 1
shows an external voltage or VDDQ
GEN
(or VDDQ_GEN in
FIG. 1
) connected through inductance L to resistors R
i
, . . . , R
n
and capacitors C
i
, . . . , C
n
, wherein the capacitors C
i
, . . . , C
n
power the internal voltages or VDDQ
internal
(or INTERNAL_VDDQ) in FIG.
1
). With this model in mind, problems are observed as being caused by inductance and resistance when it is desired to charge a relatively large capacitance in a very short time, i.e., on the order of nanoseconds (ns).
In these cases, a large amount of current is flowed involving a significant drop on the resistance. If left uncontrolled, fluctuations of the power current dropped at the resistance induce drops or overshoots of the values of the internal power VDDQ
internal
(by the inductance).
These drops and overshoots may generate variations of the values of VDDQ
internal
resulting in undesirable consequences. For example, an uncontrolled drop of VDDQ
internal
below a trigger point voltage may turn off p-mos transistors that take VDDQ as a high reference voltage. Also, an eventual VDDQ
internal
drop below the trigger point voltage may slow output switching for those transistors that have V
gate
equal to zero. This undesired effect may occur due to delays associated with waiting for the VDDQ to recover before detecting the V
out
logic value to be “1”.
The charging and discharging of the output data pin, i.e., characterized by a relatively large capacitance, is one of the situations wherein this effect may produce significant undesirable effects. To prevent these effects, current control may be provided when the output buffers are switching on.
The control of the VDDQ absorbed current may be achieved by different techniques. One technique is controlling the p-mos buffer turn on. The buffer elements are not switched on in digital mode, as is typical with traditional architectures, but their VGS absolute values rise in time with a pending control.
FIG. 2
, e.g., schematically illustrates a conventional architecture. The conventional architecture of
FIG. 2
has VDDQ
internal
connected to the p-mos (P
4
) transistors M
0
and M
3
. The p-mos transistor M
3
is connected to n-mos (N) transistor M
2
. The p-mos transistor M
0
is connected to n-mos (N) transistor M
1
. The n-mos transistors M
1
and M
2
are each also connected to ground. An input control signal data
out
(or OUT_DATA in
FIG. 2
) controls each of the p-mos transistor M
3
and the n-mos transistor M
2
. The output of the p-mos transistor M
3
controls each of p-mos transistor M
0
and n-mos transistor M
1
. The output of the p-mos transistor M
0
is connected to capacitor C
out
.
The discharge current may be controlled, as in the circuit of
FIG. 2
, by the turning to ground of the gate of the p-mos transistor M
0
when data
out
is low. In this way, current absorbed by the out buffer, when the output data changes from “0” to “1”, has a continuous profile in the time without abrupt variations.
RECOGNIZED IN THE INVENTION
It is recognized in the present invention that a determination of the value of the gate discharge current may be achieved by modifying the circuit of
FIG. 2
in different ways according to FIG.
3
. These modifications each include insertion of a device D between the output of p-mos transistor M
6
corresponding to p-mos transistor M
3
of
FIG. 2
, and n-mos transistor M
4
, corresponding to n-mos transistor M
2
of FIG.
2
. The output of p-mos transistor M
6
still controls p-mos transistor M
7
, corresponding to p-mos transistor M
0
of FIG.
2
. The n-mos transistor M
5
, corresponding to n-mos transistor M
1
of
FIG. 2
, is now controlled by the digital N-control. Specific modifications include adding a discharge resistor as the device D, as in the circuit of
FIG. 4
, or adding a mirrored current transistor as the device D, as in the circuit of FIG.
5
.
Referring to
FIG. 4
, the discharge resistor (RP) R
1
may be inserted between the output of the p-mos transistor M
10
corresponding to the p-mos transistor M
3
of
FIG. 2
, and the n-mos transistor M
8
corresponding to the n-mos transistor M
2
of FIG.
2
. The output of p-mos transistor M
10
would still control the p-mos (P
4
) transistor M
11
corresponding to the p-mos transistor M
0
of FIG.
2
. The n-mos transistor (N) M
9
of the circuit of
FIG. 4
, and corresponding to the n-mos transistor M
1
of
FIG. 2
, would be controlled by digital N-control, rather than by the output of p-mos transistor M
10
as in the circuit of FIG.
2
.
Referring to
FIG. 5
, the mirrored current transistor M
16
may be inserted between the output of the p-mos transistor M
14
corresponding to the p-mos transistor M
3
of
FIG. 2
, and the n-mos transistor M
12
corresponding to the n-mos transistor M
2
of FIG.
2
. The mirrored current transistor M
16
is controlled by I
mirror
(or I_MIRROR in FIG.
5
). The output of p-mos transistor M
14
would still control the p-mos (P
4
) transistor M
15
corresponding to the p-mos transistor M
0
of FIG.
2
. The n-mos transistor (N) M
13
of the circuit of
FIG. 5
would be controlled by digital N-control, rather than by the output of p-mos transistor M
14
as in the circuit of FIG.
2
.
The solutions described above with reference to
FIGS. 4 and 5
may solve the problem of VDDQ drop, because the buffer turn on is controlled. However, these solutions are not preferred herein for avoiding overshoot of VDDQ when C
out
is charged and the current goes to zero. These solutions do not involve an active control because the resistance value of R
1
or mirrored current value of M
16
are determined at the time the circuit is designed and are not later modifiable. It is desired to have an active control which prevents the VDDQ drop and overshoot problems described above.
SUMMARY OF THE INVENTION
In view of the above, an output buffer switch-on control is provided for avoiding internal VDDQ drop and overshoot with a limited circuital overhead. Eventual VDDQ variations are automatically corrected by active controlling implemented by an output voltage feedback arrangement.
A particularly preferred output buffer switch-on control circuit includes at least four transistors. The first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. The second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. The third transistor is controlled by the output data source and has a first terminal connected to a common voltage. The fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor and has a second terminal connected to the common voltage. The switch-on control circuit further includes a discharge current control circuit connected between a second terminal of the first transistor and a second terminal of the third transistor. The discharge current control circuit is advantageously preferably actively-controlled.
The discharge current control circuit preferably includes a discharge resistor and a mirrored current transistor. The mirrored current transistor is preferably controlled by a connection between the second terminal of the second transistor and the first terminal of th

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