Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-09
2004-07-13
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S310000
Reexamination Certificate
active
06762463
ABSTRACT:
BACKGROUND
FIG. 1
illustrates a conventional MOSFET
10
. The device is formed in a p-well or an n-well
11
formed in a silicon substrate (not shown). A channel
12
is then doped by, for example, ion implantation. A high dielectric constant (k) film
15
is then formed over the device by chemical vapor deposition (CVD) or sputtering. The gate, typically poly silicon or metal, is then formed over the high k film. Portions of the gate and the high k film are then etched away to expose source/drain regions
13
, which are then doped.
The device is annealed, typically at about 1100° C., to activate the p- and n-type dopants. During the high temperature anneal, the channel region
12
and the high k layer
15
react to form an interfacial layer
14
. The interfacial layer and the high k film together have a lower capacitance than the high k film alone. The reduced capacitance caused by interfacial layer
14
reduces the driving current of the device and thereby reduces the operating speed of the device.
SUMMARY
In accordance with a first embodiment of the invention, a MOSFET includes a well, a channel formed in the well, a high K layer overlying the channel, a buffer layer overlying the high k layer, a gate overlying the buffer layer, a blocking layer overlying the gate and two source/drain regions. In some embodiments the high k layer is an epitaxial metal oxide. In embodiments the buffer and blocking layers are epitaxial silicon. In some embodiments the gate and the source/drain regions are amorphous silicon germanium. In accordance with another embodiment of the invention, a MOSFET includes a well, a channel formed in the well, a high K layer overlying the channel, a metal gate overlying the high k layer, and two silicon germanium source/drain regions.
REFERENCES:
patent: 4466172 (1984-08-01), Batra
patent: 5880508 (1999-03-01), Wu
patent: 6198138 (2001-03-01), Hirota
patent: 6255698 (2001-07-01), Gardner et al.
patent: 6353249 (2002-03-01), Boyd et al.
patent: 6353259 (2002-03-01), Sato et al.
patent: 6362065 (2002-03-01), Swanson et al.
patent: 6368907 (2002-04-01), Doi et al.
patent: 6373114 (2002-04-01), Jeng et al.
patent: 6406945 (2002-06-01), Lee et al.
patent: 6406973 (2002-06-01), Lee
patent: 6483151 (2002-11-01), Wakabayashi et al.
patent: 2001/0020723 (2001-09-01), Gardner et al.
patent: 2002/0000607 (2002-01-01), Pfirsch
patent: 2002/0014662 (2002-02-01), Yamazaki et al.
Loke Steven
Owens Douglas W.
LandOfFree
MOSFET with SiGe source/drain regions and epitaxial gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOSFET with SiGe source/drain regions and epitaxial gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOSFET with SiGe source/drain regions and epitaxial gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3245608