Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
1999-12-28
2004-03-23
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S532000, C438S533000, C438S537000
Reexamination Certificate
active
06709959
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No.10-374717, filed on Dec. 28, 1998, the contents thereof being incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to fabrication of a semiconductor device having a shallow junction.
In the art of CMOS LSIs (large scale integrated circuits), increase of integration density, and hence increase of operational speed of the semiconductor device, has been a consistent and important target of device development. Today, LSIs are fabricated according to the so-called submicron rules or sub-quarter micron rules and the minimum pattern width in the LSI is becoming smaller than 0.2 &mgr;m.
In the CMOS LSIs having such a very large integration density, it has been recognized that the so-called short-channel effect appears conspicuously. Such a short-channel effect emerges as a result of the MOS transistor operation deviating from the classical gradual approximation model. When such a deviation appears conspicuously, there arises various problems in the transistor operation such as decrease of drain current or shifting of threshold voltage.
Conventionally, it has been recognized that such a short channel effect can be reduced by decreasing the ion implantation energy or acceleration energy in the step of forming the source or drain region such that the depth of the junction formed in the semiconductor substrate is reduced.
TABLE I summarizes the acceleration energy and dose that have been used or to be used in the ion implantation process of CMOS technology of various generations in the past or in the future.
TABLE I
device generation
180 nm
130 nm
100 nm
contact hole size (nm)
70-140
26-52
40-80
channel length (nm)
36-72
26-52
20-40
drain extension (cm
−3
)
1 × 10
19
1 × 10
19
1 × 10
20
p-drain i-i
B,2 keV
B,1 keV
B,0.5 keV
dose (cm
−2
)
8 × 10
13
8 × 10
13
8 × 10
13
n-drain i-i
P,5 keV
Sb,10 keV
Sb,7 keV
dose (cm
−2
)
3 × 10
13
1 × 10
14
1 × 10
14
Referring to TABLE I, it should be noted that the acceleration energy is reduced with the progress of the device generation and hence device miniaturization, wherein it can be seen that the use of such a reduced ion implantation energy is particularly important in the formation of the p-type drain extension structures, which are formed by injection of B into the Si substrate by an ion implantation process. In the fabrication technology of a CMOS device of the 180 nm design rule, it should be noted that an acceleration energy of about 2 keV is used for the formation of the p-type drain extension structure, while in the case of a CMOS device fabricated according to the 130 nm design rule, an acceleration energy of about 0.5 keV may be used.
Conventionally, an ion implantation process has been conducted such that impurity ions are implanted into a Si substrate through a thin oxide film formed on the surface of the Si substrate. By employing such an approach, the impurity elements that have failed to enter the substrate and remaining on the surface of the oxide film in the form of precipitates are removed easily by conducting a cleaning process or by removing the oxide film itself, and the reliability of the semiconductor device is improved.
On the other hand, such an approach to implant the impurity ions into the substrate through such an oxide film causes a problem, particularly in the advanced high-speed CMOS devices having a very shallow LDD (lightly doped drain) structure, in that it is necessary to use a relatively large energy for causing the impurity ions to reach the Si substrate after traversing through the oxide film. Because the use of large acceleration energy induces a large standard deviation in the particle energy, it should be noted that the depth of the junction formed in the Si substrate tends to become deep. This problem becomes particularly acute in the formation of the p-type diffusion region which is formed by an ion implantation of B.
FIG. 1
shows the accumulated dose of B for the case in which B is implanted to a Si substrate in the form of B
+
with an acceleration energy of 0.5 keV. It should be noted that the accumulated dose of
FIG. 1
represents the ratio of the B atoms included in the Si substrate in the region between the substrate surface and the designated depth over the entire amount of the B atoms implanted in the Si substrate. Thus, the accumulated dose is calculated from the depth profile of B in the Si substrate obtained by an SIMS (secondary ion mass spectroscopy) analysis. In view of the fact that the depth profile of B in an SiO
2
film and the depth profile of B in an Si substrate are more or less the same, the accumulation dose of
FIG. 1
can be regarded as the proportion of the B atoms captured by an SiO
2
film covering the Si substrate with a desired thickness.
In the process technology of the state of the art, an SiO
2
film can be formed on a Si substrate with reliability only when the thickness thereof is more than about 2 nm. Assuming that the thickness of the SiO
2
film is 2 nm,
FIG. 1
indicates that about 50% of the B atoms are captured by the SiO
2
film. In other words, the efficiency of B injection into the Si substrate becomes substantially poor in the process technology available today, provided that the ion implantation process is conducted through a thermal oxide film. When the efficiency of injection of the impurity element into the Si substrate is low as such, the impurity concentration level in the Si substrate cannot be increased as desired, and the diffusion region tends to show an increased resistance. Because of this, the process technology of forming a thin oxide film on a Si substrate with a thickness of less than 2 nm is now becoming a key technology in the fabrication process of extremely miniaturized, high-speed semiconductor devices characterized by a very shallow junction.
Conventionally, it has been realized that the processing of a Si substrate surface by an oxidizing agent to form a chemical oxide film is effective for forming such a desirable, very thin oxide film. For example, it is possible to form a chemical oxide film with a thickness of about 1.2 nm by treating the surface of the Si substrate by a nitric acid.
It should be noted that the wet treatment process used for forming such a chemical oxide film is generally conducted by a solution containing hydrogen peroxide. For this purpose, various chemical agents listed below in TABLE II are known, including HPM (hydrochloric peroxide mixture), SPM (sulfuric acid peroxide mixture), and APM (ammoniac peroxide mixture).
TABLE II
HPM
HCL:H
2
O
2
:H
2
O = 1:1:5 − 1:2:7 75-85° C.
SPM
H
2
SO
4
:H
2
O
2
= 4:1 high temperature
APM
NH
4
OH:H
2
O
2
:H
2
O = 1:1:6 − 1:2:8 75-85° C.
Thus, it has been thought that the desired low energy ion implantation of the impurity element may become possible by forming such a thin chemical oxide film on the surface of the Si substrate and by conducting the ion implantation process through the thin chemical oxide film.
In the experimental investigation that constitutes the foundation of the present invention, however, the inventor of the present invention has discovered unexpectedly that the diffusion of the B atoms is substantially facilitated in the Si substrate when the B atoms are introduced into the Si substrate by a low-energy ion implantation process conducted through such a thin chemical oxide film. As a result of the facilitated diffusion, the B atoms penetrates deeply into the Si substrate. Although the exact mechanism of phenomenon is not well understood at the moment, it is plausible that the point defects associated with the Si—O dangling bonds on the surface of the chemical oxide film are injected into the Si substrate at the ion implantation process together with the impurity element.
Thus, in the case the impurity ion implantation is conducted in t
Hikazutani Ken-ichi
Hori Mitsuaki
Kase Masataka
Kataoka Yoshikazu
Miyake Toshiki
Fujitsu Limited
Pham Long
Rao Shrinivas H.
Westerman Hattori Daniels & Adrian LLP
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