Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-23
2004-07-06
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S300000, C257S303000, C257S306000, C257S383000, C257S384000, C257S412000, C257S774000
Reexamination Certificate
active
06759720
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device having contact holes defined in a self-aligned manner and a method of manufacturing the same.
2. Description of the Background Art
In the field of a semiconductor device typified by a DRAM (Dynamic Random Access Memory), a design size thereof has recently been reduced with a progress in scale down thereof. With a reduction in design size, a memory device such as the DRAM or the like needs to form both contact holes (capacitor contacts) which lead to capacitors for memory cells, and contact holes (BL contacts) which lead to bit lines, as a self alignment contact (SAC) structure.
In a COB (Capacitor Over Bit-line) structure which is currently in vogue for a DRAM's structure, a capacitor contact normally has a depth of about 1 &mgr;m. By a feasible etching selection ratio or the like, it is then not always easy to form the capacitor contact having the 1 &mgr;m-depth in a suitable position in a self-aligned manner. Therefore, a method of forming first contact plugs in a self-aligned manner and defining contact holes (diameter-reduced contacts) small in diameter on the first contacts might be used as a method of manufacturing the DRAM having the COB structure. According to the method referred to above, since the depths of the contact holes to be defined at a time are reduced, difficulties accompanied by the formation of the capacitor contacts can be relieved.
FIG. 27A
is a cross-sectional view of a memory cell section of an embedded DRAM device manufactured by the conventional method referred to above.
FIGS. 27B and 27C
respectively show cross-sectional views of a CMOS (Complementary Metal Oxide Semiconductor) formed in a logic circuit section include in the embedded DRAM device. More specifically,
FIG. 27B
is a cross-sectional view of an NMOS transistor section in the logic circuit section, and
FIG. 27C
is a cross-sectional view of a PMOS transistor section in the logic circuit section, respectively.
Further,
FIGS. 28A through 28C
,
FIGS. 29A through 29C
and
FIGS. 30A through 30C
are drawings for respectively describing layouts of the embedded DRAM device in accordance with the progress of manufacturing processes. The flow of the processes used upon manufacturing the embedded DRAM device by the conventional method will be explained below with reference to these drawings.
Step 101: Insulating isolation films
12
are formed on a silicon substrate
10
. As a result, active regions designated at numerals
13
in
FIGS. 28A through 28C
are formed.
Step 102: A P-type well
14
is formed in each of a memory cell section and an NMOS transistor section. A P-type channel is introduced into a surface region of the P-type well
14
.
Step 103: An N-type well
16
is formed in a PMOS transistor section. An N-type channel (P-type channel layer in the case of a buried channel type) is introduced into a surface region of the N-type well
16
.
Step 104: A gate insulating film
24
is formed so as to cover the surfaces of the active regions.
Step 105: A conductive gate electrode film
26
, a polycide film
28
, and a silicon insulating film
30
which serves as a mask for the gate electrode film
26
, are formed over the gate insulating film
24
.
Step 106: The silicon insulating film
30
is etched by a resist mask. The gate electrode film
26
and the polycide film
28
are etched with each processed silicon insulating film
30
as a mask. In order to form an N-type impurity layer
36
and a P-type impurity layer
40
in the memory cell section, the NMOS transistor section and the PMOS transistor section respectively, impurities are introduced into those regions in a self-aligning manner with respect to gate electrodes by using masks.
Step 107: A silicon nitride film
32
is formed so as to cover the whole surface of the semiconductor wafer. As a result, transfer gates (TG)
33
covered with the silicon nitride film
32
are formed in all of the memory cell section, the NMOS transistor section and the PMOS transistor section (see FIGS.
28
A through
28
C).
Step 108: The silicon nitride film
32
for covering the NMOS transistor section and the PMOS transistor section is anisotropically etched to thereby form in those regions side walls
34
which cover the sides of the gate electrode films
26
.
Step 109: An N-type impurity and a P-type impurity are respectively introduced into the NMOS transistor section and the PMOS transistor section. As a result, an N− region
36
and an N+ region
38
are formed in the NMOS transistor section, whereas a P− region
40
and a P+ region
42
are formed in the PMOS transistor section.
Step 110: A first interlayer insulating film
44
is deposited on the whole surface of the semiconductor wafer.
Step 111: In the memory cell section, contact holes
46
are formed between the gate electrode films
26
in a self-aligned manner with the silicon nitride film
32
as a stopper film. Subsequently, etching for removing the stopper film
32
at the bottom of each contact hole is carried out to form the contact holes
46
. At this time, the side walls
34
for covering the sides of each gate electrode film
26
are formed even in the memory cell section. Using mask patterns designated at numerals
48
in
FIG. 29A
forms the contact holes
46
.
Step 112: Doped polysilicon is embedded inside the contact holes
46
to form conductive contact plugs
50
between the adjacent TGs
33
.
Step 113: A second interlayer insulating film
52
is formed over the first interlayer insulating film
44
and the contact plugs
50
.
Step 114: BL contacts
54
, which lead to their corresponding bit lines, are formed in the memory cell section, the NMOS transistor section and the PMOS transistor section. The BL contacts
54
are formed by using mask patterns designated at numerals
56
in
FIGS. 30A through 30C
.
Step 115: Contact plugs
58
are formed inside their corresponding BL contacts
54
, then bit lines
60
are patterned on the second interlayer insulating film
52
.
Step 116: A third interlayer insulating film
62
is formed so as to cover the bit lines
60
.
Step 117: Capacitor contacts
64
, which extend through the second and third interlayer insulating films
52
and
62
and are opened above the contact plugs
50
, are formed in the memory cell section. The capacitor contacts
64
are formed by using mask patterns designated at numerals
66
in
FIGS. 30A through 30B
.
Step 118: Doped polysilicon or W or the like is embedded inside the capacitor contacts
64
to thereby form conductive contact plugs
68
.
Step 119: A fourth interlayer insulating film
70
is formed over the third interlayer insulating film
62
.
Step 120: Lower electrodes
72
, which conduct to the contact plugs
68
, an insulating film
74
for covering the lower electrodes
72
, and an upper electrode
76
for covering the insulating film
74
are formed in the memory cell section. According to the conventional manufacturing method, an embedded memory device equipped with the DRAM having the COB structure is manufactured by executing the aforementioned series of processes.
With high integration of an embedded memory logic device, a source-drain region of a logic circuit section has been reduced or scaled down in recent years. Namely, the N+ region
38
shown in FIG.
27
B and the P+ region
42
shown in
FIG. 27C
have been reduced. It is therefore desirable to form not only the capacitor contacts in the memory cell section but also the BL contacts in the logic circuit section as the SAC structure as regarding the embedded memory logic device. However, the conventional method referred to above cannot form the BL contacts
54
in the logic circuit section as the SAC structure.
It is necessary for the conventional manufacturing method to deposit the silicon nitride film
32
on the silicon substrate
10
and thereafter deposit the first interlayer insulating film
44
suc
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