Space efficient interconnect test multi-structure

Details Space efficient interconnect test multi-structure Space efficient interconnect test multi-structure

2002-10-22

2004-01-20

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

Reexamination Certificate

active

06680484

ABSTRACT:

TECHNICAL FIELD OF INVENTION
The present invention relates generally to test structures utilized in semiconductor manufacturing, and, more particularly, to test structures formed in scribe lines which offer multiple testing configurations.
BACKGROUND OF THE INVENTION
As interconnect dimensions scale to smaller sizes, oxide layers become less robust, and current densities increase in today's integrated circuits, the reliability of interconnects becomes a greater concern due to, for example, metal diffusion, barrier breakdown, oxide failure, and increased electromigration effects. Electromigration (EM), which is the diffusion of atoms in an interconnect induced by an electric current, can lead to interconnect failure by voiding or extrusion at sites along the interconnect. Furthermore, electromigration is generally temperature dependent, wherein thermal gradients due to joule heating can increase the EM effects. Tensile and compressive stresses can develop in a variety ways within the interconnect, for example, due to a difference in temperature at which dielectric layers and metallization layers are processed in the formation of the circuit. Failure of the interconnect may occur, for example, once stress somewhere in the interconnect exceeds a critical stress. Therefore, test structures are conventionally incorporated into a circuit layout on a wafer. However, the test structures must be properly designed and constructed so as to detect these potential failures when tested. The test structures may also provide utility for process development and tuning, as well as for performance comparison purposes. Typically, the test structure may be formed, for example, using metal conductive layers such as aluminum or copper.
FIG. 1A
illustrates a cross-sectional view of an interconnect test structure
100
having a first conductor
105
(e.g., a cathode), a second conductor
110
, and a third conductor
115
(e.g., an anode). The second conductor
110
generally forms an interconnect line between the first conductor
105
and the third conductor
115
.
FIG. 1A
further illustrates a common failure mode, wherein voids
120
are formed near the region of the first conductor
105
due to a flow of electrical current and temperature gradients associated therewith. Voids
120
are typically paired with hillocks
125
, that is, areas of metal accumulation, downstream in the electron flow. Hillocks
125
may cause, for example, metal filaments to extend from the second conductor
110
thereby forming paths of high current leakage. If the hillocks
125
are of a sufficient magnitude, a force exerted by the hillocks in the second conductor
110
(e.g., hillocks in a metal interconnect) may crack a surrounding barrier or dielectric material. Therefore, electrical and/or thermal stress testing of various types of interconnect structures is useful for determining the current density limits that circuit design engineers use in the design of product interconnect to assure maximum performance without sacrificing reliability.
Electromigration of atoms or ions from one point to another within the metal structure may cause a void at a location originally occupied by the moving atom, or alternatively, a deposition or growth at another location of the metal. In many configurations of integrated circuits, void formation very often decreases the life of the circuit, or may even result in failure of the circuit, thereby resulting in failure of a chip or system containing the circuit. The geometry of metallic interconnect lines associated with integrated circuits are generally thin and narrow, for example, less than a few tenths of a micron in depth and less than one-tenth of a micron in width, wherein electromigration may induce a void that results in a significant decrease in cross-sectional area of the electrically conductive material across the depth of width of the conductive line. Decreasing the volume of metal in the conductive path will tend to cause an increase in electrical resistance or failure of the line, or may even result in an open-circuit line. Therefore, it is highly desirable to be able to characterize electromigration properties as well as other properties of an interconnect system so as to determine a cumulative failure distribution, a median life time to failure (MTTF), the activation energy of interfacial diffusion, grain boundary or bulk diffusion, and the current density dependence.
In the past, such characterization data has been obtained through conventional DC electromigration tests performed on a packaged test chip or by wafer-level testing. To accelerate the wear of components, the test structures should endure stress current densities above the maximum used in product designs, (e.g., one million amps per square centimeter and higher), and elevated temperatures (e.g., on the order of about 150° C. to 250° C.) Furthermore, conventional test chips, or “plug bars”, placed onto product wafers consumed significant amounts of wafer area which could otherwise be utilized for production chips. Problems associated with test chips (also called process monitor chips or “PMCs”) may furthermore involve discrepancies in field densities across a wafer. For example, an SRAM chip comprises very densely populated structures and metal layers. A PMC formed on the same wafer, on the other hand, is generally sparsely populated as compared to the SRAM chip, and processes such as chemical mechanical polishing of metal layers may have a tendency to cause dishing in metal lines.
Another problem associated with test chips is that the test is conventionally conducted after the complete assembly of the chip. In a typical manufacture of a semiconductor chip, a large number of chips are generally formed on a single semiconductive wafer. Furthermore, numerous steps are typically performed subsequent to the formation of the chips on the wafer during final assembly, such that a long period of time may elapse before the final product is completed and ready for this testing. This typically means that all of the subsequent manufacturing steps and assembly must be completed, and assembly must be at least partially complete before the conventional type of lifetime testing or characterization of the test chip can be performed to determine whether or not the metal interconnect layers are satisfactory.
In order to avoid some of the problems associated with PMCs and to optimize wafer area utilization, test structures have been moved from the usable chip areas to scribe lines. Scribe lines are the areas of a wafer which generally separate individual chips, wherein a diamond saw utilized in separating the chips generally cuts once the chip is finalized.
FIG. 1B
illustrates one prior art test structure
175
utilized for electromigration testing purposes, wherein the test structure resides within a scribe line
180
. The test structure
175
comprises a plurality of solid pads
182
, wherein a test probe (not shown) is operable to electrically contact the plurality of solid pads to induce an electrical current from a current source
184
and measure a voltage via a voltmeter
186
across the a conductive line
188
such as a bow-tie lead. The test structure
175
of the prior art, however, may suffer from several deficiencies. For example, in order to adequately accommodate the test probe, the solid pads
182
generally consume much of the width W of the scribe line, leaving only a small portion
190
available for the conductive line
188
. The portion
190
of the scribe line
180
is usually limited to accommodating a limited number of conductive lines
188
in order to avoid encroachment onto the production chip area. Furthermore, there is typically not enough available area in the scribe line for the test structures of the prior art to characterize more than a few metal layers. Since other modules also occupy typical scribe lines, such as alignment marks for lithography and modules for characterizing transistor and diode quality, there is typically not enough space for adequate scribe line structures for characte

Affiliated with

Also associated with

Rating

Space efficient interconnect test multi-structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Space efficient interconnect test multi-structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Space efficient interconnect test multi-structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3243980