Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-12-16
2004-05-04
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S391000, C257S314000, C257S315000, C257S316000, C257S338000, C257S369000
Reexamination Certificate
active
06730973
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically, it relates to a semiconductor device reducing a surface step of an interlayer dielectric film.
2. Description of the Background Art
FIG. 13
is a plan view of a conventional flash memory.
Peripheral transistors are provided around memory cells. Dummy gates are provided between the peripheral transistors and the memory cells. A plurality of interlayer dielectric films are provided on these semiconductor devices.
A method of fabricating the conventional flash memory is now described with reference to
FIGS. 14
to
23
illustrating a peripheral circuit region and a memory cell region of the flash memory.
Referring to
FIG. 14
, shallow trench isolation films (STI)
2
are provided on the surface of a silicon substrate
1
.
Referring to
FIG. 15
, a tunnel oxide film
3
is provided on the silicon substrate
1
. A first gate electrode
4
of polysilicon is formed on the tunnel oxide film
3
. The first gate electrode
4
is employed for forming floating gate electrodes.
Referring to
FIG. 16
, an ONO (Oxide-Nitride-Oxide Multilayers) film
5
, formed by an oxide film, a nitride film and an oxide film, is provided on the silicon substrate
1
to cover the surface of the first gate electrode
4
.
Referring to
FIGS. 16 and 17
, portions of the tunnel oxide film
3
, the first gate electrode
4
and the ONO film
5
located on the peripheral circuit region are removed.
Referring to
FIG. 18
, a gate oxide film
6
is formed on the peripheral circuit region. Thereafter polysilicon layers
7
, WSi layers
8
and TEOS (Tetra Ethyl Ortho Silicate) films
9
are successively formed on the silicon substrate
1
including the peripheral circuit region and the memory cell region.
FIG. 19
is a sectional view taken along the line XIX—XIX in FIG.
18
.
FIGS. 20
to
23
are sectional views also taken along the line XIX—XIX in FIG.
18
. Referring to
FIG. 19
, the polysilicon layers
7
and the WSi layers
8
are generically referred to as control gate electrodes.
Referring to
FIG. 20
, the first gate electrode
4
is patterned for forming floating gate electrodes
4
.
Referring to
FIG. 21
, side wall spacers
10
are formed on the side walls of the control gate electrode in the peripheral circuit region and those of memory cells. Then, a source line
16
is formed by etching. At this time, the TEOS films
9
are also partially scraped. A first interlayer dielectric film
11
is formed on the silicon substrate
1
, to cover the control gate electrode and the memory cells.
Referring to
FIG. 22
, the first interlayer dielectric film
11
is polished up to an intermediate stage by chemical mechanical polishing (CMP), for flattening a surface step of the first interlayer dielectric film
11
.
Referring to
FIG. 23
, contact holes
12
are formed in the first interlayer dielectric film
11
. W is embedded in the contact holes
12
for forming plugs
20
followed by formation of Al wires
13
patterned to extend in the horizontal direction, thereby completing the flash memory.
In the conventional method, the surface step of the first interlayer dielectric film
11
is flattened through the process of stopping etching the interlayer dielectric film
11
in the intermediate stage of CMP.
However, the thickness of the interlayer dielectric film
11
is remarkably dispersed in the chip due to a step caused by a gate electrode or the like located under the interlayer dielectric film
11
.
Further, the CMP process stopping etching in the intermediate stage disadvantageously results in remarkable dispersion between lots.
In another conventional method, therefore, dummy STI films
21
and a dummy gate electrode
22
are formed in order to suppress dispersion of a surface step in flattening of an interlayer dielectric film by CMP, as shown in
FIGS. 24 and 25
. Referring to
FIGS. 24 and 25
, numeral
30
denotes a gate electrode of a transistor.
FIG. 25
is a plan view, and
FIG. 24
is a sectional view taken along the line XXIV—XXIV in FIG.
25
.
While this method is carried out in order to homogeneously eliminate dispersion of a step located under the interlayer dielectric film, CMP is stopped in an intermediate stage, to disadvantageously result in dispersion of the surface step of the interlayer dielectric film.
SUMMARY OF THE INVENTION
The present invention has been proposed in order to solve the aforementioned problems, and an object thereof is to provide a semiconductor device so improved as to cause no dispersion in a surface step of an interlayer dielectric film.
Another object of the present invention is to provide a flash memory so improved as to cause no dispersion in a surface step of an interlayer dielectric film.
The semiconductor device according to the present invention comprises a memory cell region having a memory cell and a peripheral circuit region having a transistor, both provided on a semiconductor substrate, a first pattern consisting of a first conductive layer forming the aforementioned memory cell, a second pattern consisting of a film, containing nitrogen atoms, provided on the aforementioned first pattern in correspondence to the first pattern, a third pattern forming a gate electrode of the aforementioned transistor so that the height between the main surface of the aforementioned semiconductor substrate and the surface of the third pattern is lower than the aforementioned first pattern, and a fourth pattern consisting of a film, containing nitrogen atoms, provided on the aforementioned gate electrode in correspondence to the aforementioned third pattern with a larger thickness than the aforementioned second pattern. A second conductive layer is formed on the aforementioned second and fourth patterns. The thickness of a portion of an interlayer dielectric film located between the aforementioned second pattern and the aforementioned second conductive layer is smaller than the thickness of a portion of the interlayer dielectric film located between the aforementioned fourth pattern and the aforementioned second conductive layer.
According to the present invention, the thickness of the second pattern formed on the first pattern is smaller than the thickness of the fourth pattern and the thickness of the interlayer dielectric film is also small although the height of the third pattern between the main surface of the semiconductor substrate and the surface of the pattern is lower than the first pattern, whereby the second conductive layer is improved in step of a wire between the memory cell region and the peripheral circuit region to attain excellent flatness and high reliability.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6362049 (2002-03-01), Cagnina et al.
patent: 2002/0117708 (2002-08-01), Nishioka
patent: P2000-216353 (2000-08-01), None
Hibi Yasuhiro
Shimizu Satoshi
Sugihara Tsuyoshi
Renesas Technology Corp.
Tran Minhloan
Tran Tan
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