Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-08-28
2004-09-14
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S644000, C438S653000, C438S654000, C438S678000, C438S687000, C438S688000
Reexamination Certificate
active
06790773
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and processing, and in particular, to electroplating and fabrication of layers prior to electroplating.
2. Discussion of the Related Art
Integrated circuits fabricated on semiconductor substrates for very and ultra large scale integration typically require multiple levels of metal layers to electrically interconnect the discrete layers of semiconductor devices on the semiconductor chips. The different levels of metal layers are separated by various insulating or dielectric layers (also known as interlevel dielectric (ILD) layers), which have etched via holes to connect devices or active regions from one layer of metal to the next.
As semiconductor technology advances, circuit elements and dimensions on wafers or silicon substrates are becoming increasingly more dense. Consequently, the interconnections between various circuit elements and dielectric layers need to be as small as possible. One way to reduce the size of interconnection lines and vias is to use copper (Cu) as the interconnect material instead of conventionally used materials such as aluminum (Al). Because copper has lower resistivities and significantly higher electromigration resistance as compared to aluminum, copper advantageously enables higher current densities experienced at high levels of integration and increased device speed at higher frequencies. Thus, major integrated circuit manufacturers are transitioning from aluminum-based metallization technology to dual damascene copper technology.
However, the use of copper as the interconnect material presents various problems. For example, copper atoms can readily diffuse into adjacent ILD or other dielectric layers, which can compromise their integrity as insulators or cause voids in the conductors because of out-diffusion of the copper. As a result, a diffusion barrier layer is typically formed between the dielectric layer and the copper layer. Materials for the barrier layer include Tantalum (Ta), Tungsten Nitride (WN), Titanium Nitride (TiN), Tantalum Nitride (TaN), Silicon Nitride (SiN), and Tungsten (W). The barrier layer may be deposited using a conventional chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process or other known deposition process.
Dual damascene techniques rely on electroplating to fill small features (of order 100 nm in width) with copper. In order for this to work, a “seed layer” must be applied to the wafer to provide enough electrical conductance across the wafer, so that a sufficiently uniform layer can be electroplated. In order to electroplate copper, the underlying surface has to be able to conduct current across its surface since electroplating is an electrochemical process. The diffusion barrier typically has high sheet resistance, so that the current required for plating causes an excessive voltage drop between the center and edge of the wafer. Thus, a seed layer, typically copper, is deposited over the diffusion barrier. Deposition can be performed by any suitable process, such as PVD.
However, there are difficulties in forming the seed layer, due in part to contradictory requirements for the seed layer. First, it must be conductive enough across the face of the wafer that a uniform electroplating process can be carried out. A seed layer that is too thin does not achieve bulk conductivity, and electron scattering effects also decrease the effective conductivity of such thin films. Further, thin copper seed layers generally do not coat the barrier layer in a uniform manner, resulting in the inability to properly apply a subsequent electrochemically deposited copper layer. When a discontinuity is present in the seed layer, the portion of the seed layer that is not electrically connected to the bias power supply does not receive deposition during the electroplating process. This is particularly prevalent with high aspect ratio, sub-micron features, where the bottom surface and lower sidewalls of these features are especially difficult to coat using PVD. Thus, in general, thicker seed layers are desirable for uniform electroplating.
Current minimum thicknesses for copper seed layers are 30 nm with processes in the field that require less than 1 ohm per square sheet seed resistance. With improvements in electroplating technology, films as resistive as 5 ohms per square may eventually be suitable seeds, thereby reducing the minimum seed thickness to 9 nm of copper.
However, a second requirement limits the thickness of the combined barrier and seed layer on the sidewalls of the feature or vias to be filled. The limit arises because there is a maximum aspect ratio of a feature that can be successfully filled by electroplating. Presently, PVD has been used to deposit the seed layers. As shown in
FIG. 1A
, PVD forms a seed layer
10
having a much thicker layer on the planar surface (“field”) of the wafer than within the small features such as vias 20 and trenches, i.e., the deposition is non-conformal. The thicker material in the field allows current to be conducted across the wafer, while there is sufficient copper in the features to allow electroplating in the features. With lower aspect ratio features, e.g., <3:1, the opening of feature stays open long enough to allow a void-free fill with the electroplating.
But successive reduction in feature sizes has meant that there is increasing difficulty in this process. When the seed layer is formed on the sidewalls as well as the bottom of the feature, the electroplating process deposits the metal on both surfaces within the feature.
FIG. 1A
shows the opening of the feature being “closed off” with seed layer deposition by PVD. With higher aspect ratio features, the electroplated metal growth on the wall tends to close off the feature at the aperture opening before the feature has been completely filled, resulting in a void
30
forming within the feature, as shown in FIG.
1
B. The void changes the material and operating characteristics of the interconnect feature and may cause improper operation and premature breakdown of the device. Even directional PVD such as that carried out using a Hollow Cathode Magnetron (HCM) source gives films with a slight overhang. Thus, with current processes, relatively thin copper seed layers are necessary to fill high aspect ratio features void-free.
However, also with current technology, there is a limit of about 15 nm on the total thickness of material deposited on a via sidewall before electroplating, although this thickness is expected to decrease, down to about 12 nm for test structures at the 45 nm technology node. This thickness includes the barrier layer and any other layers needed before electroplating. Assuming that these other layers take up about 3 nm, about 8 nm of copper are available for the seed. For a layer that is about 100% conformal, such as those deposited electrolessly, by thermal CVD, or by atomic layer deposition (ALD), the field conductivity requirement necessitates an effective resistivity of less than 4 microohm-cm for the seed layer.
Effective resistivities at the thickness under consideration are considerably greater than bulk resistivities because of electron scattering at the metal surfaces. Also, the topology of the wafer surface serves to further increase the voltage drop from the center to the edge of the wafer. As a result, only copper and silver satisfy all requirements, of which copper would be more generally accepted. Another requirement is that the seed layer must enable electroplating with good adhesion. However, it is not yet known how such a conformal copper layer can be deposited with good adhesion over presently accepted barrier layers.
Clearly if the barrier and seed are one and the same then the thickness allocated for the barrier and seed is all available for this layer. For a given sheet resistance, then, a more resistive seed material may be used. So, a directly platable barrier with approximately 10 microohm-cm resistivity can be contemplated.
The expected obsolescenc
Drewery John S.
Powell Ronald A.
Chen Tom
MacPherson Kwok & Chen & Heid LLP
Nguyen Thanh
Novellus Systems Inc.
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