Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-13
2004-04-20
Vu, Hung (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S383000, C257S388000, C257S413000
Reexamination Certificate
active
06724057
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having a gate electrode and a method of fabricating the same.
2. Description of the Prior Art
A salicide (self-aligned silicide) process is generally known as a process for reducing the resistance of a gate electrode and source/drain regions of a MOS transistor. In this salicide process, a low-resistance metal silicide film is formed on the gate electrode and the source/drain regions in a self-aligned manner.
When employing the aforementioned salicide process in a step of forming a MOS transistor, extremely high-grade technique is required for setting conditions in this step. If a heat treatment (annealing) temperature is excessive, for example, silicide films grow also on side wall spacers, to disadvantageously result in defective short-circuiting (bridging) across the gate electrode and the source/drain regions.
FIG. 18
is a sectional view of a conventional semiconductor device for illustrating defective bridging. Defective bridging in the conventional semiconductor device is now described in detail with reference to FIG.
18
. In the conventional semiconductor device, field oxide films
102
are formed on element isolation regions of a silicon substrate
101
. A pair of source/drain regions
109
are formed on an element forming region enclosed with the field oxide films
102
, to hold a channel region therebetween. A gate electrode
104
consisting of a polycrystalline silicon film is formed on the channel region through a gate insulator film
103
. Side wall spacers
108
are formed on both side walls of the gate electrode
104
.
In order to apply the salicide process to the conventional semiconductor device having the aforementioned structure, a Ti film
105
is first formed on the overall surface. Thereafter heat treatment is performed for simultaneously forming metal silicide films
106
on the upper surface of the gate electrode
104
and the surfaces of the source/drain regions
109
. If the heat treatment (annealing) temperature is excessive in this case, metal silicide films
106
a
abnormally grow on the side wall spacers
108
, to disadvantageously short-circuit the gate electrode
104
and the source/drain regions
109
.
When the heat treatment (annealing) temperature is too small contrarily to the above, the silicide films
106
so insufficiently grow that the resistance cannot be sufficiently reduced by the salicide process.
Thus, the range of the conditions for setting the heat treatment is narrow in the conventional salicide process, to disadvantageously result in small process tolerance (process margin).
In order to cope with such an inconvenience that the resistance cannot be sufficiently reduced by the salicide process, Japanese Patent Laying-Open No. 10-65171 (1998) proposes a method of supplying a sufficient silicide film to a gate electrode. According to this proposed technique, the gate electrode is formed by two layers of a polysilicon layer and a first Ti silicide layer while a second Ti silicide layer is formed on the gate electrode and source/drain regions. Thus, the first and second TI silicide layers define a thick silicide layer for the gate, so that the gate electrode can be formed with a sufficient silicide film as compared with the general salicide process.
Also in the aforementioned proposed technique, however, defective bridging may be caused across the gate electrode and the source/drain regions when forming the second Ti silicide layer, and it is difficult to solve the problem of such defective bridging. In general, therefore, defective short-circuiting (defective bridging) must regularly be taken into consideration and hence the process margin (process tolerance) is disadvantageously reduced.
When forming contact holes
113
a
and
113
b
in an interlayer isolation film
113
covering the overall surface by etching upon employment of the salicide process as shown in
FIG. 19
, the etching may not be stopped in the metal silicide film
106
formed on the gate electrode
104
due to the difference between the thicknesses of portions of the interlayer isolation film
113
located on the source/drain regions
109
and the gate electrode
104
.
In this case, the contact hole
113
b
passes through the metal silicide film
106
to reach the gate electrode
104
, and further reaches the gate insulator film
103
at the worst. In this case, the gate insulator film
103
is damaged to deteriorate the characteristics of the gate electrode
104
. When the contact hole
113
b
passes through the metal silicide film
106
to reach the gate electrode
104
, it follows that an upper-layer wire comes into contact only with the side surfaces of the metal silicide film
106
and hence the contact area between the upper-layer wire and the metal silicide film
106
is reduced. Thus, contact characteristics are also disadvantageously deteriorated.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of effectively preventing a gate electrode and impurity regions from defective short-circuiting and reducing the resistance of the gate electrode and the impurity regions.
Another object of the present invention is to prevent a contact hole formed on the gate electrode from punch-through in the aforementioned semiconductor device.
Still another object of the present invention is to provide a method of fabricating a semiconductor device capable of readily forming a low-resistance compound layer by increasing process tolerance.
A semiconductor device according to an aspect of the present invention comprises a pair of impurity regions, a first gate film, a second gate film, a second compound layer and a reaction preventing film. The pair of impurity regions are formed on the main surface of a semiconductor substrate at a prescribed interval to hold a channel region therebetween. The first gate film is formed on the channel region through a gate insulator film. The second gate film is formed on the first gate film, and consists of a first compound layer. The second compound layer is formed on the surfaces of the impurity regions. The reaction preventing film is formed on the second gate film for preventing reaction between the first compound layer and the second compound layer. In the present invention, the term “semiconductor substrate” indicates a wide concept including not only a general semiconductor substrate but also a semiconductor thin film or the like.
In the semiconductor device according to the aforementioned aspect, the reaction preventing film for preventing reaction between the first compound layer and the second compound layer is so provided that the first compound layer and the second compound layer are formed independently of each other without reaction, whereby the first compound layer and the second compound layer are prevented from connection. Thus, the gate electrode and the impurity regions can be effectively prevented from defective short-circuiting. The first compound layer and the second compound layer are formed independently of each other without reaction, whereby process tolerance is increased. Thus, the first and second compound layers can be readily formed in lower resistance as compared with the prior art, for consequently reducing the resistance of the gate electrode and the impurity regions. Thus, the speed of the semiconductor device can be increased.
In the semiconductor device according to the aforementioned aspect, the reaction preventing film preferably includes a conductive film consisting of a material selected from a group consisting of a low-resistance metal, a high melting point metal and a high melting point metal compound. When formed by such a conductive film, the reaction preventing film serves as parallel resistance of the gate electrode, whereby the resistance of the gate electrode can be further reduced. Consequently, the speed of the semiconductor device can
Ibara Yoshikazu
Okayama Yoshio
McDermott & Will & Emery
Sanyo Electric Co,. Ltd.
Vu Hung
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