Surfing logic pipelines

Details Surfing logic pipelines Surfing logic pipelines

2002-10-17

2004-07-27

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S121000

Reexamination Certificate

active

06768342

ABSTRACT:

TECHNICAL FIELD
The invention relates to logic circuits and, in particular to multi-stage digital pipelines.
BACKGROUND
Synchronous logic circuits have one or more stages of combinational logic. Logic signals pass through each stage in one clock cycle. Logic signals are latched after each stage. In synchronous logic circuits the maximum clock speed is determined by the slowest path through the combinational logic of any stage.
Wave pipelined logic circuits have been proposed. A review discussing such logic circuits is provided in W. P. Burleson, M. Ciesielski et al.
Wave pipe/lining: A tutorial and research survey
, IEEE Trans on VLSI Systems, 6(3):464-74, September, 1998. Wave pipelined logic circuits suffer from the disadvantage that timing uncertainty grows monotonically as events propagate through gates or other logic elements. Thus, such circuits must either operate at lower speeds or with fewer logic stages.
It is a standard technique to provide latches at points in pipelined logic circuits. Latches can hold data values and restructure signals propagating in such circuits. However, latches introduce latency.
There is a need for faster logic circuits.
SUMMARY OF THE INVENTION
The invention relates to logic circuits. One aspect of the invention provides a surfing pipelined logic circuit. The logic circuit has a timing system which provides a timing signal sequentially to each of a plurality of logic blocks. The logic blocks are connected in a series and may have a linear configuration or a ring configuration. Each of the logic blocks has a latency which is variable in response to the timing signal. When the timing signal is not present, the latency is longer than a timing delay which occurs between the timing system applying the timing signal to the logic block and the timing signal applying the logic signal to a next one of the logic blocks. When the timing signal is present, the latency is shorter than the timing delay. The timing system may comprise a timing path carrying timing signals. The timing path may have a number of nodes connected to control inputs of corresponding ones of the logic blocks.
Other aspects of the invention provide various surfing logic elements which may be used in surfing logic circuits.
Yet another aspect of the invention provides a logic pipeline comprising a series of logic stages each having a latency. An overall latency of the logic pipeline is less than a sum of the latencies of the logic stages.
Further aspects of the invention and features of specific embodiments of the invention are described below.


REFERENCES:
patent: 5300831 (1994-04-01), Pham et al.
patent: 5392423 (1995-02-01), Yetter
patent: 5889979 (1999-03-01), Miller, Jr. et al.
patent: 6590424 (2003-07-01), Singh et al.

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