Static information storage and retrieval – Read/write circuit – With shift register
Reexamination Certificate
2001-08-31
2004-04-20
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
With shift register
C365S230030
Reexamination Certificate
active
06724665
ABSTRACT:
BACKGROUND
Passive element memory arrays, such as anti-fuse diode cell arrays, require a high-voltage and high-current programming voltage source due to the large number of leakage paths in the array and the high voltage required to program the element conductivity. The write power dissipation is dominated by the power of the programming voltage source, and the write power increases the temperature of the memory. As the temperature of the diodes increases, the diode leakage current and the write power further increase, and this feedback can cause thermal run-away and failure of the memory. While large sub-arrays are more efficient in area because support circuits are shared by more memory cells, large sub-arrays are usually associated with high leakage current. For example, in high-density anti-fuse diode memory arrays with contiguous memory cell sub-arrays of N-by-N cells stacked in multiple layers, the leakage current increases by N
2
as N increases. To reduce the chance of thermal run-away, the memory array can be subdivided into smaller sub-arrays to decrease the number of memory cells that are simultaneously accessed. However, this design can increase the cost per unit of storage capacity and can result in a relatively slow memory device.
There is a need, therefore, for a memory device and method that will avoid thermal run-away while maintaining a relatively low cost and high data rate.
SUMMARY
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims.
By way of introduction, the preferred embodiments described below provide a memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array.
Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
REFERENCES:
patent: 3851316 (1974-11-01), Kodama
patent: 4592027 (1986-05-01), Masaki
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 4646269 (1987-02-01), Wong et al.
patent: 4698788 (1987-10-01), Flannagan et al.
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4873669 (1989-10-01), Furutani et al.
patent: 5107139 (1992-04-01), Houston et al.
patent: 5149199 (1992-09-01), Kinoshita et al.
patent: 5276649 (1994-01-01), Hoshita et al.
patent: 5278796 (1994-01-01), Tillinghast et al.
patent: 5359571 (1994-10-01), Yu
patent: 5383157 (1995-01-01), Phelan
patent: 5410512 (1995-04-01), Takase et al.
patent: 5784328 (1998-07-01), Irrinki et al.
patent: 5835396 (1998-11-01), Zhang
patent: 5890100 (1999-03-01), Crayford
patent: 5925996 (1999-07-01), Murray
patent: 5940340 (1999-08-01), Ware et al.
patent: 5961215 (1999-10-01), Lee et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6034918 (2000-03-01), Farmwald et al.
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6070222 (2000-05-01), Farmwald et al.
patent: 6185712 (2001-02-01), Kirihata et al.
patent: 6212121 (2001-04-01), Ryu et al.
patent: 6236587 (2001-05-01), Gudesen et al.
patent: 6373768 (2002-04-01), Woo et al.
patent: 6385074 (2002-05-01), Johnson et al.
patent: 6560152 (2003-05-01), Cernea
“A 14ns 1Mb CMOS SRAM with Variable Bit-Organization,” Wada et al., 1988 IEEE International Solid-State Circuits Conference, pp. 252-253 (Feb. 19, 1988).
Kleveland Bendik
Scheuerlein Roy E.
Brinks Hofer Gilson & Lione
Lebentritt Michael S.
Matrix Semiconductor Inc.
Nguyen Tuan T.
LandOfFree
Memory device and method for selectable sub-array activation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory device and method for selectable sub-array activation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device and method for selectable sub-array activation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3239645