Semiconductor device with solid state image pickup element

Details Semiconductor device with solid state image pickup element Semiconductor device with solid state image pickup element

2002-10-24

2004-04-20

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Responsive to non-electrical signal

Electromagnetic or particle radiation

C257S222000, C257S225000, C257S226000

Reexamination Certificate

active

06724060

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including an element isolation insulating film for isolating an element forming region and a manufacturing method thereof.
2. Description of the Background Art
Conventionally, as an example of a semiconductor device having an element isolation insulating film, a semiconductor device having a solid-state image pickup element has been used. In the following, a conventional semiconductor device will be described, in conjunction with the semiconductor device having the solid-state image pickup element.
FIG. 20
shows a circuit configuration of the solid-state image pickup element having a CMOS (Complementary Metal Oxide Semiconductor) type image sensor. As shown in
FIG. 20
, the solid-state image pickup element has a unit pixel or a unit cell C arranged in matrix. In addition, in the solid-state image pickup element, each of unit cells C is connected to a vertical shift register VS and a horizontal shift register HS.
Each unit cell C has a photodiode PD, a transfer switch M
1
, a reset switch M
2
, an amplifier M
3
and a selection switch M
4
. Photodiode PD attains a function corresponding to a photoelectric conversion and storage portion converting incident light to electric charges and storing the resultant charges. Transfer switch Ml attains a function to transfer the charges to amplifier M
3
.
Transfer switch M
1
is controlled by a signal from vertical shift register VS. Reset switch M
2
resets photodiode PD by providing the stored charges to a ground electrode. Amplifier M
3
amplifies the magnitude of an electrical signal generated by transferring the charges. When selection switch M
4
is selected by the vertical shift register and a horizontal shift register, a source region is electrically connected to a drain region, and selection switch M
4
outputs an electrical signal to the outside.
Here, each of transfer switch M
1
, reset switch M
2
, amplifier M
3
and selection switch M
4
is fabricated with a MOS transistor.
FIG. 21
is a top view showing a specific configuration of a region R in
FIG. 20
, and
FIG. 22
is a cross-sectional view along the line XXII—XXII in FIG.
21
.
As shown in
FIGS. 21 and 22
, on the surface of a P-type semiconductor substrate
102
, an element isolation insulating film
103
is formed with LOCOS (LOCal Oxidation of Silicon). Further, on the surface of P-type semiconductor substrate
102
, photodiode PD, transfer switch M
1
and reset switch M
2
are arranged side by side.
Photodiode PD is fabricated by a PN junction of P-type semiconductor substrate
102
with an N-type impurity diffusion region (an N-type active region)
104
. In the upper portion of N-type impurity diffusion region
104
(in the vicinity of surface of P-type semiconductor substrate
102
), a P-type impurity diffusion region (a P-type active region)
105
is formed. P-type impurity diffusion region
105
is formed to such a depth that a depletion layer of the PN junction of P-type semiconductor substrate
102
with N-type impurity diffusion region
104
will not reach the lower surface of P-type impurity diffusion region
105
.
Transfer switch M
1
has an N-type source region
104
, an N-type drain region (an N-type active region, represented as FD (Floating Diffusion) because it sometimes floats during operation)
106
a
and a gate electrode layer
108
a.
N-type source region
104
and N-type drain region
106
a
are formed in P-type semiconductor substrate
102
, spaced apart from each other by a prescribed distance. Gate electrode layer
108
a
is formed on a gate insulating layer
107
above a portion lying between N-type source region
104
and N-type drain region
106
a
in P-type semiconductor substrate
102
.
Note that N-type impurity diffusion region
104
of photodiode PD and N-type source region
104
of transfer switch M
1
represent the same region, and that they are merely called differently, from the viewpoint of each element.
Reset switch M
2
has a pair of N-type source/drain regions
106
a
and a gate electrode layer
108
b.
The pair of N-type source/drain regions
106
a
are formed on the surface of semiconductor substrate
102
, spaced apart from each other by a prescribed distance. Gate electrode layer
108
b
is formed on a gate insulating layer (not shown) above a region lying between the pair of N-type source/drain regions
106
a.
Note that N-type drain region
106
a
of transfer switch M
1
and one of N-type source/drain regions
106
a
of reset switch M
2
represent the same region, and that they are merely called differently, from the viewpoint of each element.
As shown in
FIG. 22
, N-type drain region
106
a,
which is a floating diffusion region FD of the solid-state image pickup element, is in contact with an end portion of an element isolation insulating film
103
. A stress is produced in the end portion of element isolation insulating film
103
due to an action in forming the same. The stress produces an interface level (an interface state) in the end portion in a direction parallel to the main surface of P-type semiconductor substrate
102
of element isolation insulating film
103
.
In addition, a depletion layer is formed in the PN junction where N-type drain region
106
a
and P-type semiconductor substrate
102
are joined. If the depletion layer contains a portion where an interface level of the end portion of element isolation insulating film
103
is present, a leakage current is produced along a lower surface of element isolation insulating film
103
. The produced leakage current will lower the performance of the solid-state image pickup element.
A problem caused in the floating diffusion region of the solid-state image pickup element will be described more specifically, with reference to
FIGS. 23 and 24
. In
FIG. 23
, only an N-type impurity diffusion region
205
as the floating diffusion region of the solid-state image pickup element and a field oxide film
202
as the element isolation insulating film formed by oxidation of the main surface of a P-type semiconductor substrate
201
are shown.
As shown in
FIG. 23
, field oxide film
202
is formed to a prescribed height and depth above and under the main surface of P-type semiconductor substrate
201
. N-type impurity diffusion region
205
is formed in an element forming region surrounded by field oxide film
202
. As shown in
FIG. 24
, N-type impurity diffusion region
205
is formed by impurity injection to the main surface of P-type semiconductor substrate
201
, using field oxide film
202
as a mask.
Therefore, an end portion of field oxide film
202
is in contact with an end portion of N-type impurity diffusion region
205
. Accordingly, as shown in
FIG. 23
, the PN junction formed with P-type semiconductor substrate
201
and N-type impurity diffusion region
205
will contact the end portion of field oxide film
202
, that is, what is called a “bird's beak” portion
202
a.
Consequently, a depletion layer
210
formed in the vicinity of the PN junction contains an interface level present portion. Therefore, the leakage current caused by a level at an interface of bird's beak portion
202
a
with N-type impurity diffusion region
205
and P-type semiconductor substrate
201
will be produced, resulting in lower performance of the solid-state image pickup element.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device, which suppresses an occurrence of a leakage current caused by a portion, undesirably included in a depletion layer, where a level is present in an interface of an element isolation insulating film with a semiconductor substrate, and a manufacturing method of the semiconductor device.
A semiconductor device according to the present invention includes a first impurity diffusion region provided in a semiconductor substrate and including at least one impurity diffusion region having an impurity of a first conductivity type; an element isolation insulating film provided in the first im

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