Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2001-02-16
2004-04-27
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S401000, C713S500000, C713S502000, C713S600000, C714S704000, C714S709000, C714S762000
Reexamination Certificate
active
06728894
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to adjusting a clock signal and, more particularly, to a disk drive that adjusts a data sampling clock signal based on detected bits.
BACKGROUND
Phase-locked loops (PLLs) operate in a system, such as a disk drive, to synchronize the system and to improve signal-to-noise (SNR) ratios in the system. In a disk drive, an analog signal is read from a storage medium, such as a computer hard disk, and is sampled using an analog-to-digital (A/D) converter driven by a clock signal. If the clock signal is out of phase with the analog signal, errors may occur in the data detected from the resulting waveform.
SUMMARY
In general, in one embodiment, the invention is directed to adjusting a clock signal. This aspect features receiving a data stream, detecting a bit in the data stream using a first amount of data in the data stream, adjusting the clock signal based on the detected bit, detecting the bit in the data stream using a second amount of data in the data stream, the second amount of data comprising more data than the first amount of data, and correcting the clock signal if a result of initial detecting differs from a result of subsequent detecting. By virtue of this aspect, it is possible to making timing decisions quickly without suffering a significant reduction in decision accuracy.
This aspect may include one or more of the following features. The clock may be adjusted by providing the detected bit to a phase-locked loop and adjusting the clock signal using the phase-locked loop. Adjusting the clock may include generating a first waveform using the detected bit, generating a second waveform from the data stream, obtaining a phase difference between the first and second waveforms, and changing a phase of the clock signal to compensate for the phase difference. The phase difference may be incorporated into an averaged phase difference and the clock signal may be changed using the averaged phase difference.
The bit may be detected by determining whether the bit is a zero or a one or by determining a probability that the bit is a zero and a probability that the bit is a one. The subsequent detecting may also include determining whether the bit is a zero or a one or determining a probability that the bit is a zero and a probability that the bit is a one.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features and advantages of the invention will be apparent from the following description, drawings and claims.
REFERENCES:
patent: 5452325 (1995-09-01), Brown et al.
patent: 6236343 (2001-05-01), Patapoutian
patent: 2002/0087910 (2002-07-01), McEwen et al.
Han Ke
McEwen Peter
Patapoutian Ara
Sonntag Jeffrey L.
Veiga Eduardo
Lee Thomas
Maxtor Corporation
Patel Nitin C
Sigmond David M.
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