Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2002-06-28
2004-09-21
Tsai, H. Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S150000
Reexamination Certificate
active
06794227
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing an SOI (silicon-on-insulator) substrate wafer for use in the microelectronics industry. More particularly, the invention relates to a method of producing an SOI wafer by depositing a polysilicon layer on a substrate wafer, annealing this wafer in pure or dilute oxygen ambient, and recrystallizing the amorphous or polysilicon layer to become monocrystalline through high temperature annealing.
BACKGROUND OF THE INVENTION
Conventionally, there are two popular methods of fabricating wafers having an SOI structure. One method is a SIMOX method (separation by implanted oxygen), wherein a high concentration of oxygen atoms are implanted into a substrate wafer, and the wafer is then subjected to a high temperature heat treatment process to induce the implanted oxygen to form an oxide layer. The other method involves wafer bonding, wherein two wafers, both having a mirror polished finish and at least one containing an oxide layer on the surface to be bonded, are bonded together without the use of adhesive, and one of the wafers is then subjected to a thinning step.
In the SIMOX method, the thickness of the SOI layer, which will become the active device layer, is controlled by controlling the voltage of the implanting equipment. The advantage of the SIMOX process is that the thickness uniformity of the layer is easily controlled. The SIMOX process is expensive however, and is limited to single-wafer processing.
In the wafer bonding techniques, two silicon wafers are produced through standard wafer processing steps up to and including mirror polishing at least the surfaces to be bonded together. At least one of the wafers containing the mirror polish is subjected to an oxidation process. The two mirror-polished surfaces, at least one containing the oxide layer, are then brought into contact with each other, and the wafers are subjected to a thermal treatment cycle to increase the bonding strength. Subsequently one of the wafers is subjected to a thinning process. This thinning step can be accomplished by surface grinding or chemical etching, typically followed by a polishing step to ensure the surface of the thinned wafer is sufficiently smooth to ensure proper utilization in the device fabrication processes. This thinning process has several significant disadvantages, however. First, the thinning process is quite time consuming and costly to perform. Up to several hundred microns of material must be removed and disposed of in order get an SOI layer of a usable thickness. The thinning methods also have limitations in controlling the thickness uniformity of the thinned SOI layer, due in large part to limitations in the mechanical machining equipment used. Second, a large amount of silicon is wasted due to the thinning process, where the vast majority of material of one of the bonded wafers is simply removed and disposed of.
A significant improvement on the bonding method, known as the Smart-Cut method, has recently drawn attention. In this method, one of the two wafers to be bonded is subjected to ion implantation wherein hydrogen ions and rare gas ions are implanted at high levels such that a bubble layer exists within the wafer that is to become the SOI layer. Again, at least one of the wafer surfaces is subjected to an oxide formation step. The wafers are then bonded together through a thermal process. The thermal process in this case not only assists in bonding the two surfaces together, but also serves to assist in delaminating the ion implanted wafer at the plane of the implantation. The bonded wafer is then left with an oxide layer, and a thin silicon layer from the ion implanted wafer. The remains of the ion-implanted wafer can then be repolished and reused, or simply discarded. Obviously, cost savings and time savings are realized by the elimination of a grinding or etching thinning step. The surface of the bonded wafer is then treated to a touch polish or surface termination step to improve the surface roughness of the SOI layer.
One significant problem that occurs with any of the above-mentioned techniques revolves around the use of CZ, or Czochralski grown crystals. A wafer produced by the CZ method usually contains a defect known as COP (Crystal Originated Particles), which originate during crystal growth, and remain in crystal during the wafering stages of manufacture. Since COP defects remain in crystal, attempts have been made to grow an epitaxial layer on the surface of the wafer to be bonded, with the anticipation of grinding or removing the entire substrate wafer, such that only the epitaxial layer becomes the SOI layer. This added step provides a high quality silicon for the SOI layer, but costs even more than standard bonding techniques in both processing time and equipment, and is still limited to the quality of the thinning process with respect to surface thickness and thickness uniformity.
Another problem that may occur with wafers produced using the CZ technique is related to the oxygen concentration trapped in the crystal growth. To circumvent this problem, wafers manufactured from crystals grown using the FZ (Float Zone) technique have been used. Because of the different method of crystal growth, there is very little oxygen concentration within a crystal manufactured using the FZ technique. However, the design limitations of the FZ technique make it increasingly difficult, if not impossible, to grow crystals of large diameter such as 200 mm or 300 mm. This limitation does not make FZ an attractive alternative, due to the trend of increasing crystal diameters used.
Each method and/or wafer type described above has various advantages and disadvantages over the other techniques mentioned. The present invention has been accomplished to provide a method of manufacturing an SOI wafer that eliminates the problems associated with COP defects and oxygen, increase productivity over the known methods while reducing costs, and provide a high quality SOI layer.
SUMMARY OF THE INVENTION
The present invention relates to fabricating a buried oxide or oxynitride layer found in SOI wafers. In the method of the present invention, a substrate wafer is prepared through standard wafering techniques up to and including polishing at least one surface of the wafer. The polished wafer surface is then cleaned using standard SC1/SC2 cleaning methods to remove any native oxide layers and to clean the surface. A polysilicon layer is then grown on the polished surface of the substrate wafer, with the thickness of the polysilicon layer being controlled by deposition time and temperature. An anneal in oxygen ambient is then performed to accumulate oxygen, and nitrogen if desired, in the buried layer at the interface between the polished surface of the substrate wafer and the polysilicon layer. Finally, a high-temperature anneal in an oxygen/argon ambient gas mixture is used to form the buried oxide layer.
Various embodiments of the present invention provide that any of the steps utilized (cleaning, deposition of polysilicon, oxidation, or high temperature annealing) can be accomplished in batch production or in single wafer production equipment, and may be accomplished in any combination thereof.
According to the method of the present invention, SOI wafers having good thickness uniformity and excellent quality can be provided. Similarly, the cost of producing excellent quality SOI wafers can be significantly reduced by employing various embodiments of the present invention.
REFERENCES:
patent: 4889829 (1989-12-01), Kawai
patent: 5045488 (1991-09-01), Yeh
patent: 5376579 (1994-12-01), Annamalai
patent: 5650353 (1997-07-01), Yoshizawa et al.
patent: 5998281 (1999-12-01), Aga et al.
patent: 6140210 (2000-10-01), Aga et al.
patent: 6224668 (2001-05-01), Tamatsuka
patent: 6238990 (2001-05-01), Aga et al.
patent: 6239004 (2001-05-01), Aga et al.
patent: 6245645 (2001-06-01), Mitani et al.
patent: 6284629 (2001-09-01), Yokokawa et al.
patent: 6306730 (2001-10-01), Mitani et al.
patent: 6362076 (2002-03-01), Inazuki et
Anderson Douglas G.
SEH America Inc.
LandOfFree
Method of producing an SOI wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of producing an SOI wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of producing an SOI wafer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3238925