Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-10-08
1999-08-17
Coleman, Eric
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711149, G06F 1200
Patent
active
059405970
ABSTRACT:
A technique for periodically updating entries in a look-up table for directing data packets through a multi-port bridge in a local area network. For packets received during a first period, the number of the port receiving the packet is stored with the address of the node which generated the packet in a first memory and in a second memory. During the first period, the first memory is utilized for directing packets through the multi-port bridge. At the end of the first period, a third memory is cleared. For packets received during a second period, the number of the port receiving the packet is stored with the address of the node which generated the packet in the second memory and in the third memory. During the second period, the second memory is utilized for directing packets through the multi-port bridge. At the end of the second period, the first memory is cleared. For packets received during a third period, the number of the port receiving the packet is stored with the address of the node which generated the packet in the first memory and in the third memory. During the third period, the third memory is utilized for directing packets through the multi-port bridge. At the end of the third period, the second memory is cleared. This sequence is repeated such that no entry more than two periods old is utilized for directing a packet through the multi-port bridge, however, the age of each entry is not tracked.
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Coleman Eric
Sony Corporation
Sony Electronics Inc.
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