Data processing: generic control systems or specific application – Generic control system – apparatus or process – Digital positioning
Reexamination Certificate
2002-09-11
2004-01-06
Von Buhr, Maria N. (Department: 2125)
Data processing: generic control systems or specific application
Generic control system, apparatus or process
Digital positioning
C700S121000, C438S008000, C438S401000, C438S462000, C257S797000
Reexamination Certificate
active
06675053
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to photolithography processes for manufacturing integrated circuits. More particularly, the invention relates to a system for measurement of overlay error between a wafer pattern and a reticle pattern projected onto the wafer.
BACKGROUND OF THE INVENTION
As shown in
FIG. 1
, modern electronic devices
1
have integrated circuits
2
which include multiple layers
3
,
4
of circuitry features formed on a semiconductor substrate
5
. Photolithography is used to form these layers. A reticle is used in the manufacture of each layer of circuitry. Patterns on the reticles are designed to be placed on a pre-defined grid located on dies or scribe channels. The patterns are not always placed correctly on the grid leading to overlay errors between successively used reticles.
A high degree of alignment must be maintained between layers to ensure that circuit elements are properly registered with each other. Alignment is important because semiconductor manufacturing involves small feature dimensions. Present manufacturing processes routinely reach critical dimensions of 0.5 microns. The critical dimension is the smallest separation allowed between circuit elements. Even minute alignment errors can render an integrated circuit unusable.
Alignment refers to the process of registering a layer's reticle to a wafer. Several methods of alignment are known. For instance, in the dark field alignment method, alignment targets on the wafer are illuminated by an alignment illumination source. Light from the alignment illumination source floods the wafer surface and is back-scattered by edges of the wafer target and reflected by the wafer target itself. The intensity and position of back-scattered radiation is detected and compared with the position of the alignment targets on the reticle to determine the degree of alignment between the mask and wafer.
Overlay is an after-exposure measure of how accurately the alignment process was carried out. Overlay is the measure of success in the alignment process after a dependent layer or area has been exposed and developed. In the simplest form, the overlay process consists of comparing the location of an image in a second, or dependent, layer to an image in a first, or reference, layer. The degree to which the dependent layer was accurately aligned to the reference layer is determined by the degree to which the dependent image overlays the reference image. Any offset of the images demonstrates a mis-alignment.
The overall alignment and registration of a set of reticles developed for the production of a particular integrated circuit is often checked prior to actual production in an off-line procedure using a silicon test wafer. This measurement may be accomplished using a box within a box technique. In this technique, a rectangular box in the dependent layer is exposed on a similar, but larger, box on the reference layer. Overlay is measured by comparing the dimensions between the boxes on opposite sides, i.e., by measuring how well centered the smaller boxes are inside the larger boxes.
Construction of an overlay target pair
10
is illustrated in FIG.
2
. When the reference layer of circuitry is produced on the test wafer using a reference layer reticle, a large reference box
12
is etched into the substrate. During the printing of the dependent layer of circuitry using a dependent layer reticle, a small box
14
is deposited in hardened photoresist. The position of the small box
14
of photoresist in the dependent layer is compared to the position of the etched large box
12
in the reference layer to determine the overlay error between the dependent and reference layers. If the layers are perfectly aligned, the small box
14
will be precisely centered within the large box
12
. The degree to which the small box
14
is not centered within the large box
12
is a measure of the overlay error between the dependent and reference layers. Measurement of the overlay error is accomplished with hardware and software packages known in the art.
It is not uncommon for many layers of circuitry to be manufactured into a chip. Depending on the architecture of the integrated circuit, each circuitry layer can connect to adjacent layers or more remote layers. Each connection between layers creates an alignment dependency. There are multiple dependencies in a typical integrated circuit. These multiple dependencies between layers can be represented as a string of required targets. A typical overlay target string is illustrated in FIG.
3
. In this figure, the reference layers are placed in the right column and dependent layers are placed in the left column. Each horizontal pairing represents a dependent layer's dependence on a reference layer. In this target string a first layer
20
is manufactured into the chip. Two successive, dependent layers
50
and
41
must be aligned with layer
20
as indicated by the first and second pairings of the overlay target string. (Layer numbering is typically independent of the order of the layers.) Layer
50
, the second layer manufactured into the chip, becomes a reference layer in turn with three dependent layers
41
,
38
and
43
that must be aligned with it, as shown in the third through fifth pairings.
The construction of the target string through the layers is illustrated in FIG.
4
. In
FIG. 4
each column to the left of the vertical line represents the target activity of each layer of the integrated circuit. The column to the right of the vertical line represents the cumulative target string. Two reference box targets
200
,
202
, one for each of layer
20
's dependent layers, are etched into the test wafer. During the printing of layer
50
, a dependent box target
500
is deposited in hardened photoresist. The overlay error between layer
20
and
50
is determined based on the degree to which dependent box target
500
is centered with reference box target
200
. As the testing process continues, three reference box targets
504
,
506
and
508
, one each for each layer
50
's dependent layers, are etched into the wafer.
During the printing of layer
41
, two dependent box targets
412
,
414
are deposited in hardened photoresist. The overlay error between layer
41
and layers
20
and
50
can be determined based on the degree to which dependent box targets
412
and
414
are centered within reference box targets
202
and
504
, respectively.
During the printing of layer
38
, a dependent box target
386
is deposited in hardened photoresist. The overlay error between layer
38
and layer
50
can be determined based on the degree to which dependent box target
386
is centered within reference box target
506
. During the printing of layer
43
, a dependent box target
438
is deposited in hardened photoresist. The overlay error between layer
43
and layer
50
can be determined based on the degree to which dependent box target
438
is centered within reference box target
508
.
The target string for the entire process of five layers with five interdependencies is represented in the right column. The target string consists of five reference-dependent target pairs A-E.
The technology used in analyzing overlay targets requires certain layout rules. References boxes are typically 20 microns square and are laid out on the surface of the chip at a 50 micron pitch. The dependent boxes are 10 microns square. Thus, when multiple layers are processed on a wafer, a significant area of the wafer must be dedicated to placement of target strings. Real estate on the surfaces of integrated circuits is limited and expensive, however. What is required then, is an improved layout for target strings in multi-layer photolithographic processes for integrated circuits that conserves the area required for overlay measurement.
SUMMARY OF THE INVENTION
The invention concerns a method for laying out reference targets for measurement of overlay error in the manufacture of multi-layer integrated circuits.
According to one aspect of the invention, a reference tar
Baluswamy Pary
Bossart Tim H.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Von Buhr Maria N.
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