Sense amplifier arrangement for semiconductor memory device

Details Sense amplifier arrangement for semiconductor memory device Sense amplifier arrangement for semiconductor memory device

2002-01-22

2004-01-13

Le, Thong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S207000

Reexamination Certificate

active

06678194

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to a semiconductor memory device and more specifically to an arrangement of sense amplifiers and memory cell arrays in a semiconductor memory device.
BACKGROUND OF THE INVENTION
It is a continuing goal to make a semiconductor memory device finer in order to provide more memory cells on a single device, decrease chip size and/or reduce manufacturing costs. One such method of decreasing the chip size of a semiconductor memory device, such as a dynamic random access memory (DRAM), is to provide a plurality of cell arrays that have a row of shared sense amplifiers disposed between. Each shared sense amplifier selectively receives data from a bit line pair from one memory cell array or from a bit line pair from the adjacent memory cell array.
Referring now to
FIG. 1
, a plan view of a conventional semiconductor memory device is set forth in a schematic diagram and given the general reference character
500
.
Conventional semiconductor device
500
of
FIG. 1
has shared sense amplifiers arranged in a row between adjacent memory cell arrays. Each shared sense amplifier is connected to two bit line pairs (four bit lines).
Conventional semiconductor device
500
consists of cell arrays (
521
,
522
,
523
and
524
). Each cell array (
521
,
522
,
523
and
524
) has a plurality of bit lines.
Cell array
521
includes bit lines (
601
to
624
). Bit lines (
601
to
624
) are arranged in bit line pairs (
601
-
602
to
623
-
624
). Each bit line pair (
601
-
602
to
623
-
624
) includes a bit line and a complementary bit line. Likewise, cell arrays (
522
to
524
) respectively include bit lines (
625
to
648
,
649
to
672
, and
673
to
696
). Bit lines (
625
to
648
) are arranged in bit line pairs (
625
-
626
to
647
-
648
). Bit lines (
649
to
672
) are arranged in bit line pairs (
649
-
650
to
671
-
672
). Bit lines (
673
to
696
) are arranged in bit line pairs (
673
-
674
to
695
-
696
). Likewise, each bit line pair (
625
-
626
to
647
-
648
,
649
-
650
to
671
-
672
, and
673
-
674
to
695
-
696
) includes a bit line and a complementary bit line.
Cell array
521
has a row of unshared sense amplifiers (
531
to
536
) on one side and a row of shared sense amplifiers (
537
to
542
) on the other side. Bit line pairs (
601
-
602
to
623
-
624
) are respectively, alternatively connected to unshared sense amplifiers (
531
to
536
) and shared sense amplifiers (
537
to
542
). More specifically, bit line pair (
601
-
602
) is connected to unshared sense amplifier
531
, bit line pair (
602
-
603
) is connected to shared sense amplifier
537
, and so on, and bit line pair (
623
-
624
) is connected to shared sense amplifier
542
.
Cell array
522
has the row of shared sense amplifiers (
537
to
542
) on one side and a row of shared sense amplifiers (
543
to
548
) on the other side. Bit line pairs (
625
-
626
to
647
-
648
) are respectively, alternatively connected to shared sense amplifiers (
543
to
548
) and shared sense amplifiers (
537
to
542
). More specifically, bit line pair (
625
-
626
) is connected to shared sense amplifier
543
, bit line pair (
627
-
628
) is connected to shared sense amplifier
537
, and so on, and bit line pair (
647
-
648
) is connected to shared sense amplifier
542
.
Cell array
523
has the row of shared sense amplifiers (
543
to
548
) on one side and a row of shared sense amplifiers (
549
to
554
) on the other side. Bit line pairs (
649
-
650
to
671
-
672
) are respectively, alternatively connected to shared sense amplifiers (
543
to
548
) and shared sense amplifiers (
549
to
554
). More specifically, bit line pair (
649
-
650
) is connected to shared sense amplifier
543
, bit line pair (
651
-
652
) is connected to shared sense amplifier
549
, and so on, and bit line pair (
671
-
672
) is connected to shared sense amplifier
554
.
Cell array
524
has a row of unshared sense amplifiers (
555
to
560
) on one side and a row of shared sense amplifiers (
549
to
554
) on the other side. Bit line pairs (
673
-
674
to
695
-
696
) are respectively, alternatively connected to unshared sense amplifiers (
555
to
560
) and shared sense amplifiers (
549
to
554
). More specifically, bit line pair (
673
-
674
) is connected to unshared sense amplifier
555
, bit line pair (
675
-
676
) is connected to shared sense amplifier
549
, and so on, and bit line pair (
695
-
696
) is connected to shared sense amplifier
554
.
Conventional semiconductor device
500
includes sense amplifier drivers (
501
to
510
).
Unshared sense amplifiers (
531
to
533
) are connected to sense amplifier driver
501
.
Unshared sense amplifiers (
534
to
536
) are connected to sense amplifier driver
502
. Shared sense amplifiers (
537
to
539
) are connected to sense amplifier driver
503
. Shared sense amplifiers (
540
to
542
) are connected to sense amplifier driver
504
. Shared sense amplifiers (
543
to
545
) are connected to sense amplifier driver
505
. Shared sense amplifiers (
546
to
548
) are connected to sense amplifier driver
506
. Shared sense amplifiers (
549
to
551
) are connected to sense amplifier driver
507
. Shared sense amplifiers (
552
to
554
) are connected to sense amplifier driver
508
. Shared sense amplifiers (
555
to
557
) are connected to sense amplifier driver
509
. Shared sense amplifiers (
558
to
560
) are connected to sense amplifier driver
510
.
In semiconductor memory device
500
, cell arrays (
521
to
524
) are conceptualized as (N−1)
th
to (N+2)
th
cell arrays, respectively, where N is an integer of 2 or more. Sense amplifier drivers (
501
and
502
), and unshared sense amplifiers (
531
to
536
) are conceptualized as a (N−1)
th
sense amplifier section. Sense amplifier drivers (
503
and
504
), and shared sense amplifiers (
537
to
542
) are conceptualized as a N
th
sense amplifier section. Sense amplifier drivers (
505
and
506
), and shared sense amplifiers (
543
to
548
) are conceptualized as a (N+1)
th
sense amplifier section. Sense amplifier drivers (
507
and
508
), and shared sense amplifiers (
549
to
554
) are conceptualized as a (N+2)
th
sense amplifier section. Sense amplifier drivers (
509
and
510
), and unshared sense amplifiers (
555
to
560
) are conceptualized as a (N+3)
th
sense amplifier section.
In conventional semiconductor memory device
500
, when N
th
cell array
522
is activated, for example, N
th
sense amplifier section (including sense amplifier drivers (
503
and
504
) is activated and (N+1)
th
sense amplifier section (including sense amplifier drivers (
505
and
506
) is activated. In this way, sense amplifiers (
537
to
548
) are activated to read data on bit lines (
625
to
648
) connected to the selected side of sense amplifiers (
537
to
548
). In
FIG. 1
, the sense amplifiers (
537
to
548
) activated when N
th
cell array
522
is activated are illustrated with hatching.
In conventional semiconductor memory device
500
, each sense amplifier section is configured to include one sense amplifier for every two bit line pairs (four bit lines), so that adjacent sense amplifiers in one sense amplifier section are not connected to adjacent bit lines. Instead adjacent sense amplifiers in each sense amplifier section are electrically separated by two bit lines (one bit line pair).
Also, adjacent sense amplifiers in each sense amplifier section are driven by a different sense amplifier driver (
501
to
510
). For example, although N
th
sense amplifier section includes sense amplifiers (
537
to
542
), sense amplifiers (
537
to
539
) are connected to be driven by sense amplifier driver
503
and sense amplifiers (
540
to
542
) are connected to be driven by sense amplifier driver
504
. Such an arrangement of sense amplifiers arranged to be driven by separate sense amplifier drivers is disclosed in Japanese Laid-Open Patent Publication No. Hei 9-45879, entitled “Dynamic RAM.”
By providing a sense amplifier driver for ever

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