Profiled retaining ring for chemical mechanical planarization

Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – For liquid etchant

Reexamination Certificate

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C156S345120

Reexamination Certificate

active

06716299

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to chemical mechanical planarization, and more particularly to a non-coherent profiled retaining ring for reducing non-uniformity during a chemical mechanical planarization process.
2. Description of the Related Art
In the fabrication of semiconductor devices, planarization operations are often performed, which can include polishing, buffing, and wafer cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. Patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide.
As semiconductor fabrication is an automated process, techniques have been developed to ensure fabrication robots properly align wafers within each step of wafer fabrication. For example, wafers are often notched at a point along the edge of the wafer to facilitate proper wafer alignment. Other alignment techniques include the use of flatted wafers, wherein an edge of the wafer is flat (not rounded). However, as described in greater detail subsequently, flatted wafers often generate problems during particular wafer manufacturing processes, such as during wafer planarization.
As more metallization levels and associated dielectric layers are formed, the need to planarize the dielectric material increases. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal planarization operations are performed to remove excess metallization. Further applications include planarization of dielectric films deposited prior to the metallization process, such as dielectrics used for shallow trench isolation or for poly-metal insulation. One method for achieving semiconductor wafer planarization is the chemical mechanical planarization (CMP) process.
In general, the CMP process involves holding and rubbing a typically rotating wafer against a moving polishing pad under a controlled pressure and relative speed. CMP systems typically implement orbital, belt, or brush stations in which pads or brushes are used to scrub, buff, and polish one or both sides of a wafer. Slurry is used to facilitate and enhance the CMP operation. Slurry is most usually introduced onto a moving preparation surface and distributed over the preparation surface as well as the surface of the semiconductor wafer being buffed, polished, or otherwise prepared by the CMP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface.
As mentioned above, techniques have been developed to ensure fabrication robots properly align wafers within each step of wafer fabrication. Conventional CMP systems often have little trouble when polishing notched wafers. Unfortunately, conventional CMP systems generally do not perform satisfactorily when processing flatted wafers.
FIG. 1
is a diagram showing a conventional carrier head
100
holding a flatted wafer
102
. As illustrated in
FIG. 1
, the wafer
102
is held in position during CMP processing by a conventional retaining ring
104
, which surrounds the wafer
102
. Generally, a small distance delta exists between the edge of the wafer
102
and the interior surface of the retaining ring
104
to allow the wafer
102
to be easily positioned within the carrier head
100
. During a CMP operation the carrier head
100
rotates in a direction
110
along a polishing belt or table, depending on the type of CMP system utilizing the carrier head
100
. As mentioned above, the polishing surface moves beneath the wafer
102
during polishing.
The movement of the polishing surface causes a friction force
106
, which is applied to the wafer
102
. Because of the delta between the wafer
102
and the retaining ring
104
, the friction force
106
pushes the wafer
102
in the direction of the polishing surface movement until the wafer is stopped by the retaining ring
104
. Once the wafer
102
contacts the retaining ring
104
, a reaction force
108
is generated from the retaining ring
104
. Generally, the reaction force
108
does not contributed greatly to uniformity errors when the rounded edges of the wafer
102
come into contact with the retaining ring
104
. However, because of the delta between the wafer
102
and the retaining ring
104
, the wafer
102
rotates within the retaining ring
104
. As a result, the comers of the flatted portion of the wafer
102
eventually come into contact with the retaining ring
104
, as illustrated in FIG.
2
.
FIG. 2
is an illustration showing prior art carrier head
100
when the flatted section of the wafer
102
contacts the conventional retaining ring
104
. As above, the wafer
102
is held in position by the conventional retaining ring
104
, which surrounds the wafer
102
. However, as shown in
FIG. 2
, the wafer
102
has rotated such that two corners
200
of the flatted section of the wafer
102
are both in contact with the retaining ring
104
.
The contact of the two corners
200
with the retaining ring
104
generates reaction forces
202
concentrated at the comers
200
of the flatted section of the wafer
102
. As is well known to those skilled in the art, each reaction force
202
can be split into component forces
204
a
and
204
b
for easier analysis. In particular, each reaction force
202
comprises a first force component
204
a
, which is directed along the rounded edge of the wafer
102
, and a second force component
204
b
, which is directed along the flatted edge of the wafer
102
. Hence, the second force components
204
b
of the reaction force
202
from each comer
200
are opposed to each other, causing stress to wafer
102
from the corners
200
. Unfortunately, the opposing second force components
204
b
cause the wafer
102
buckle near the flatted section, as shown by area
206
. As a result, the buckled flatted wafer section
206
is pushed into the polishing surface, causing over-polishing in the flatted wafer section
206
as illustrated in FIG.
3
.
FIG. 3
is an illustration showing a flatted wafer
102
resulting from a CMP operation using a conventional retaining ring. When the flatted wafer section
206
is buckled and, as a result, pushed into the polishing surface, non-uniformity results. In particular, the flatted area
206
of the wafer
102
is polished with an increased removal rate relative to the remaining sections of the wafer
102
because of the additional force present in the flatted area
206
during polishing. As a result, the flatted area
206
of the wafer
102
is over-polished. The resulting non-uniformity can have a dramatic negative effect on the devices formed on the wafer, often causing the entire wafer to be discarded.
In view of the foregoing, there is a need for CMP techniques and apparatuses that allow flatted wafers to be polished with an essentially uniform removal rate. In particular, the apparatuses should not allow over-polishing of the flatted section and should allow essentially uniform planarization during a CMP process.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a non-coherent profiled retaining ring that allows planarization of flatted wafers without over-polishing the flatted region of the wafer. In one embodiment, a retaining ring for use in a CMP system is disclosed that includes an annular retaining ring capable of holding a flatted wafer in position during a CMP operation. The flatted wafer has a first corner and a second corner disposed on a flatt

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