Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-03-23
2004-07-13
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S757000, C714S758000, C714S807000
Reexamination Certificate
active
06763495
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a CRC code calculation circuit and a CRC code calculation method for calculating a CRC code from received variable-length data in the receiving side of data.
2. Description of the Related Art
A CRC (Cyclic Redundancy Check) has been conventionally used in order to detect an error of data in digital communication. Here, the CRC means a method for detecting an error of data by comparing a CRC code calculated in a CRC code calculation circuit of the data receiving side with a CRC code calculated in the data sending side.
In recent years, for example, high-speed variable-length data communication for conducting end-to-end communication with low-speed variable-length data (PPP frame) overlaid on a high-speed data frame (SONET/SDH frame) as POS (PPP Over SONET/SDH) has been used widely.
Then, the CRC has been introduced as an error detection method of data in the high-speed variable-length data communication. Here, a CRC code calculation circuit calculates a CRC code from n byte parallel data inputted.
FIG. 5
is a block diagram showing a conventional CRC code calculation circuit
100
.
As shown in
FIG. 5
, the CRC code calculation circuit
100
of four-byte parallel data generally comprises a four-byte parallel CRC code calculation circuit
2
, a one-byte serial CRC code calculation circuit
11
, a two-byte parallel CRC code calculation circuit
12
, a three-byte parallel CRC code calculation circuit
13
, and an SEL
5
.
The four-byte parallel CRC code calculation circuit
2
, whose details are described later, is a circuit for calculating a CRC code from data (see {circle around (1)}, {circle around (2)} of
FIG. 6
) except for a final stage having a residual portion of four-byte parallel data inputted.
Also, the four-byte parallel CRC code calculation circuit
2
outputs the calculated CRC code to the SEL
5
and also outputs data (see {circle around (3)} of
FIG. 6
) of the final stage having a residual portion to one calculation circuit selected by a selection circuit (not shown) of the one-byte serial CRC code calculation circuit
11
, the two-byte parallel CRC code calculation circuit
12
and the three-byte parallel CRC code calculation circuit
13
.
The one-byte serial CRC code calculation circuit
11
, the two-byte parallel CRC code calculation circuit
12
and the three-byte parallel CRC code calculation circuit
13
are circuits for respectively calculating a CRC code from data of the final stage having a residual portion inputted from the four-byte parallel CRC code calculation circuit
2
. Also, each the calculation circuit
11
,
12
and
13
respectively latches the calculated CRC code and outputs the code to the SEL
5
.
The SEL (selector)
5
selectively outputs any one of the CRC codes inputted from each the CRC code calculation circuit
2
,
11
,
12
and
13
.
Next, a procedure of calculating a CRC code from four-byte parallel data will be described with reference to FIG.
6
.
As shown in
FIG. 6
, four-byte parallel data D is data having a frame length of ten bytes and consists of three stages of {circle around (1)} (
1
to
4
), {circle around (2)} (
5
to
8
) and {circle around (3)} (
9
to
10
). Here, the data {circle around (3)} of the final stage consists of a residual portion
9
,
10
and invalid data (shaded areas in
FIG. 6
) of two bytes.
First, the data {circle around (1)}, {circle around (2)} of the four-byte parallel data D is inputted to the four-byte parallel CRC code calculation circuit
2
. Then, the four-byte parallel CRC code calculation circuit
2
calculates a CRC code A from the inputted four-byte parallel data {circle around (1)}, {circle around (2)} and outputs the calculated CRC code A to the SEL (omission of being shown in the drawing).
Next, the data {circle around (3)} of the four-byte parallel data D is inputted to the two-byte parallel CRC code calculation circuit
12
selected by a selection circuit (not shown) since the residual portion (
9
,
10
) is two bytes. Here, when the residual portion of the four-byte parallel data {circle around (3)} is one-byte, the four-byte parallel data {circle around (3)} is inputted to the one-byte serial CRC code calculation circuit
11
. Also, when the residual portion is three bytes, the four-byte parallel data {circle around (3)} is inputted to the three-byte parallel CRC code calculation circuit
13
.
Then, the two-byte parallel CRC code calculation circuit
12
calculates a CRC code B from the inputted four-byte parallel data {circle around (3)} and outputs the calculated CRC code B to the SEL (omission of being shown in the drawing).
Further, the SEL (not shown) selects and outputs any one of the inputted CRC codes A and B.
By the way, the four-byte parallel data of a target for CRC code calculation is variable in the frame length and the residual portion of the final stage changes from one-byte to three bytes, so that a CRC code cannot be calculated by only the four-byte parallel CRC code calculation circuit
2
.
As a result of this, the conventional CRC code calculation circuit
100
provides a plurality of the calculation circuits
11
,
12
,
13
in order to calculate the residual portion of the final stage of the four-byte parallel data, so that a circuit scale became large and manufacturing costs were high.
SUMMARY OF THE INVENTION
An object of the invention is to achieve miniaturization of a CRC code calculation circuit for calculating a CRC code from byte parallel data which is variable-length data and reduce manufacturing costs.
In order to solve the problems, according to a first aspect of the invention, there is provided a CRC code calculation circuit (for example, a CRC code calculation circuit
10
shown in
FIG. 2
) for calculating a CRC code from parallel data having a residual portion in a final stage, and the CRC code calculation circuit comprises:
parallel calculation means (for example, a four-byte parallel CRC code calculation circuit
2
shown in
FIG. 2
) for calculating a CRC code in parallel from the parallel data except the final stage;
conversion means (for example, a byte serial conversion circuit
3
shown in
FIG. 2
) for converting the final stage into serial data;
serial calculation means (for example, a one-byte serial CRC code calculation circuit
4
shown in
FIG. 2
) for calculating a CRC code in serial from the CRC code calculated by the parallel calculation means and the serial data converted by the conversion means; and
CRC code selection means (for example, a SEL
5
shown in
FIG. 2
) for selecting a desired CRC code from the plural CRC codes calculated by the parallel calculation means and the serial calculation means.
According to the first aspect of the invention, in a CRC code calculation circuit for calculating a CRC code from parallel data having a residual portion in a final stage, by parallel calculation means, a CRC code is calculated in parallel from the parallel data except the final stage, and by conversion means, the final stage is converted into serial data, and by serial calculation means, a CRC code is calculated in serial from the CRC code calculated by the parallel calculation means and the serial data converted by the conversion means, and by CRC code selection means, a desired CRC code is selected from the plural CRC codes calculated by the parallel calculation means and the serial calculation means.
Also, as a second aspect of the invention, by final stage detection means (for example, a control part
6
shown in
FIG. 2
) further provided in the CRC code calculation circuit as defined in claim
1
, the final stage of the parallel data is detected and the conversion means converts the detected final stage into serial data.
According to a fourth aspect of the invention, there is provided a CRC code calculation method for calculating a CRC code from parallel data having a residual portion in a final stage, and the method comprises:
a final stage detection step of detecting the final stage of the parallel data;
a conversion step of converting
Inoue Takao
Mori Kenjiro
Suzuki Masayoshi
Ando Electric Co. Ltd.
De'cady Albert
Fish & Richardson P.C.
Gandhi Dipakkumar
LandOfFree
CRC code calculation circuit and CRC code calculation method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with CRC code calculation circuit and CRC code calculation method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CRC code calculation circuit and CRC code calculation method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3235774