Semiconductor device with silicon-carbon-oxygen dielectric...

Details Semiconductor device with silicon-carbon-oxygen dielectric... Semiconductor device with silicon-carbon-oxygen dielectric...

2002-12-12

2004-04-13

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S765000, C438S798000

Reexamination Certificate

active

06720255

ABSTRACT:

CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to semiconductor devices and methods and are more particularly directed to improving adhesion to a silicon-carbon-oxygen dielectric layer.
Semiconductor devices are prevalent in countless different aspects of contemporary society, and as a result, the marketplace for such devices continues to advance at a fairly rapid pace. This advancement is evident in many respects and relates to semiconductor devices either directly or indirectly as well as the methods for forming such devices. For example, the advancement affects numerous device attributes and increases the need for attention to such attributes during design and manufacturing, where such attributes include device size, reliability, yield, and cost. These aspects as well as others are addressed by the prior art and are further improved upon by the preferred embodiments as detailed below.
By way of further background, the preferred embodiments relate to adhesion to dielectric layers in semiconductor devices. More specifically, the preferred embodiments relate to a dielectric layer that includes all of silicon, carbon, and oxygen and the adhesion of such a layer to a barrier layer that is to operate as a barrier between the dielectric layer and a metal such as copper. Turning first to the dielectric layer having silicon, carbon, and oxygen, such materials are sometimes combined in a film known as organo-silicon glass (“OSG”), which is commercially available from Novellus and Applied Materials. OSG layers are attractive for various reasons known in the art, such as a favorable (i.e., relatively low) dielectric constant. Turning next to copper, its use is becoming more preferred in the art, particularly as an interconnect metal, because relative to previously used metals, such as aluminum, copper provides lower resistance and, hence, greater reliability.
Given the preceding, when copper is used in a same device as an OSG layer, typically a barrier layer is formed between the copper and OSG. The barrier layer prevents or reduces the undesirable chance of the Copper diffusing into the dielectric. However, in connection with the preferred embodiments, the present inventors have determined that when placing a barrier layer between OSG and copper, the adhesion of the barrier layer to the OSG has been unacceptable. For example, such adhesion has been empirically evaluated using several known testing techniques, and those techniques have demonstrated that the barrier layer will detach from the OSG, thereby failing to serve its underlying purposes as a barrier to a subsequently-formed copper layer/device. For example, tape testing has been used, wherein a semiconductor wafer, on which a barrier layer is formed on an OSG layer, is scribed and then tape is applied to the wafer and removed to determine if the layers remain intact. Under such testing, cracks have been found to form at the interface of the barrier layer and the OSG layer, thereby demonstrating qualitatively that the bond between the two layers is unacceptable. As another example, four point bend testing has been performed, wherein a same type of semiconductor wafer as described above is subjected to flexing forces at its ends, in combination with other forces applied more centrally to the wafer. Using this test, a quantitative measure is made to determine the end-applied force at what there is a failure between the OSG and the barrier layer, where such a failure may occur as a crack or break of the barrier layer, or the barrier layer may delaminate from the OSG layer. As a final test, chemical mechanical polishing (“CMP”) may be applied to the above-described wafer. This test is sometimes preferred in that it represents an actual manufacturing step, since CMP is often used to planarize various layers before subsequent processing steps. In any event, under CMP, the present inventors also have observed failures between an adjacent OSG and barrier layer.
In view of the above, the present inventors provide below alternative embodiments for improving upon various drawbacks of the prior art.
BRIEF SUMMARY OF THE INVENTION
In one preferred embodiment, there is a method of fabricating an electronic device formed on a semiconductor wafer. The method forms a dielectric layer in a fixed position relative to the wafer, where the dielectric layer comprises an atomic concentration of each of silicon, carbon, and oxygen. After the forming step, the method exposes the electronic device to a plasma such that the atomic concentration of carbon in a portion of the dielectric layer is increased and the atomic concentration of oxygen in a portion of the dielectric layer is decreased. After the exposing step, the method forms a barrier layer adjacent at least a portion of the dielectric layer.
Other aspects are also disclosed and claimed.


REFERENCES:
patent: 6511909 (2003-01-01), Yau et al.

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