Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2003-07-28
2004-09-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
Reexamination Certificate
active
06790707
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a method of preparing a test specimen for testing of the bonding strength of a layer of additive material to a crystalline substrate, or testing of the bonding strength of one layer of additive material to a second layer of additive material, where both layers of additive material overlie a crystalline substrate.
BRIEF DESCRIPTION OF THE BACKGROUND ART
The manufacture of semiconductor devices typically involves the deposition of layers of additive material (i.e., thin films) on a crystalline semiconductor substrate, such as single-crystal silicon or gallium arsenide. Adhesion of the layers of additive material to each other and to the semiconductor substrate is very important, because delamination of any one of the layers can lead to device failure. Therefore, the bonding strength of the various layers of additive material to each other and to the semiconductor substrate is critical, and testing is carried out as a part of manufacturing process development and quality control.
The general concepts of thin film adhesion measurements for multi-layered thin film structures have been described in several papers. See, for example, “Adhesion and Debonding of Multi-Layer Thin Film Structures”, R. H. Dauskardt et al.,
Engineering Fracture Mechanics,
pp. 141-162 (1998); “Quantitative Measurement of Interface Fracture Energy in Multi-Layer Thin Film Structures”, Q. Ma et al.,
Proceedings of MRS Annual Meeting,
San Francisco, Calif., pp. 3-14 and 91-96 (1995); “Adhesion and Reliability of Copper Interconnects with Ta and TaN Barrier Layers”,M. Lane et al.,
J. Mat. Res.,
15(1), pp. 203 -211 (2000).
With respect to thin films overlying relatively thick crystalline substrates, the measurement of adhesion energy is primarily concerned with the macroscopic, or effective work of fracture per unit area required to separate an interface of interest. This may be quantified in terms of the critical strain energy release rate (debonding energy), G
c
(typically in J/m
2
), which is a function of material properties, such as the interfacial chemistry, adjacent microstructures, and elastic-plastic stress-strain behavior. G
c
is also a function of mechanical properties, such as the loading mode mixity near to the debond tip (the ratio of shear to normal stresses). Other design parameters, including the surface morphology (roughness) and the thickness of adjacent thin film layers, may also have an important effect on adhesion.
The interface fracture resistance during debonding essentially depends upon two different energy absorbing processes. These are G
o
the near-tip work of fracture, and the energy dissipation which occurs in a zone surrounding the debond. In a region close to the debond crack tip, the intrinsic near-tip work of fracture G
o
provides a direct measure of the fracture process at the interface. Factors which contribute to G
o
include chemical bonding parameters from across the bond interface and/or micromechanical processes associated with the fracture mechanism.
Alternatively, in some instances, depending on the structure being tested, an energy dissipation zone appears due to factors such as the plasticity of adjacent ductile layers and the interaction of the debond faces behind the debond tip, G
zone
. Interaction mechanisms may involve frictional sliding of uneven contacting surfaces and even plastic stretching of unbroken ligaments across the fracture surfaces. Since these energy dissipation mechanisms typically act behind the debond crack tip, their effect increases with initial debond extension, until a steady-state interface fracture resistance is achieved. While such resistance curve behavior is often observed during interface failure, due to the scale of thin film structures, experimental detection of these effects is difficult and generally precluded. As a result, what is finally measured is:
G
c
=G
o
+G
zone
(units: J/m
2
).
A significant limitation of many thin film adhesion measurement techniques, such as the peel test, blister test, indentation test, is that during debonding, residual stresses in the thin film relax and modify the measured adhesion energy. The effects of such relaxation on the measured adhesion values can be large, and although such effects can mathematically be included in an analysis, it is frequently difficult to accurately measure residual film stress of a very thin film present on a rigid substrate.
Thin film stress relaxation can be significantly reduced by preparing a sandwich structure where two pieces of the thin film on a rigid substrate are bonded together with the thin film being tested in the center of the sandwich. A small contribution to the measured value of G
c
will arise from elastic curvature of one of the rigid substrates supporting the thin film after debonding. However, the contribution of this effect to the debond driving energy has been shown to be minimal. Another advantage of the sandwiched sample configuration is the enablement of fracture mechanics-based tests to indicate the characteristics of subcritical debond-growth rate behavior which is associated with enviromnentally assisted or fatigue processes.
A commonly used adhesion test in the semiconductor industry is the four-point (bending) adhesion test. Apparatus for performing the four-point adhesion test is available, for example, from Dauskardt Technical Services (Menlo Park, Calif.). Referring to
FIG. 1
, which is a schematic top view of an assembly
130
used to perform the four-point adhesion test, a test specimen
100
is placed between dowel pins (
114
,
116
,
118
,
120
) within bending fixture
111
members
110
and
112
. The length of test specimen
100
must be longer than the distance A between dowels
114
and
116
, and typically ranges from about 30 mm to about 50 mm. Sandwich test specimen
100
consists of two semiconductor structures (
102
and
104
), each having a length of about 40 mm, a width of about 5 mm, and a thickness of about 0.8 mm. The two semiconductor structures have been sandwiched together, face-to-face, and bonded with a layer
106
of an epoxy adhesive in the middle of the sandwich. Typically, the epoxy adhesive layer thickness is about 5 &mgr;m to about 20 &mgr;m; however, depending on the clamping pressure placed on the sample during cure of the epoxy adhesive, the bonding layer may be as thin as about 2 &mgr;m. Bonding time and temperature and general sample preparation techniques are typically provided by the supplier of the epoxy adhesive. Higher bond temperatures and longer times within the specifications of the manufacturer's recommended process generally produce stronger bonds.
After bonding of the sandwich test specimen
100
, the exposed surfaces
103
and
105
of the sandwich test specimen
100
are typically a highly crystalline material, such as single crystal silicon or gallium arsenide. The upper surface
103
shown in
FIG. 1
is then notched or grooved in a straight line across the entire width of the surface
103
, from edge to edge. A notch (shown in
FIG. 4D
, for example) or a groove is typically cut into semiconductor structure
102
using a diamond saw. The notch or groove
108
is typically formed to have a maximum depth of about 500 &mgr;m into the surface
103
of semiconductor structure
102
. Since the crystalline substrate material typically has a thickness of about 700 &mgr;m, about 200 &mgr;m of thickness of the crystalline substrate material remains overlying the thin film which is to be tested for adhesion to the crystalline substrate, for example.
The adhesion test is performed by applying a load to test fixture
111
at a constant displacement rate (about 0.01-0.5 &mgr;m/sec) to bend the test specimen
100
, while carefully observing a loaddisplacement curve generated by the load cell which has a chassis and a piezoelectric actuator. A schematic illustration of a load-displacement curve is shown in
FIG. 2
, which is a graph
200
showing load (on the vertical axis
202
) versus displacement (on the horizontal axi
Applied Materials Inc.
Church Shirley L.
Stevenson Andre′ C.
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