Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-28
2004-07-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S285000
Reexamination Certificate
active
06768160
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to flash memory cell devices and more specifically, to improvements in charge distribution of charge trapping memory cell devices.
BACKGROUND OF THE INVENTION
Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory), utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO
2
), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain up to 6.0eV of kinetic energy which is more than sufficient to cross the 3.2eV Si-SiO
2
energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the SiO
2
interface under the influence of the control gate electric field and will cross the tunnel oxide and reach the floating gate—where such electrons remain as a stored charge.
Once programmed, the negative charge on the floating gate disburses across the semi conductive gate and has the effect of increasing the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate.
During a “read” of the memory cell, the programmed, or non-programmed, state of the memory cell can be detected by detecting the magnitude of the current flowing between the source and drain at a predetermined control gate voltage.
More recently dielectric memory cell structures have been developed. Each dielectric memory cell is characterized by a vertical stack of an insulating tunnel layer, a charge trapping dielectric layer, an insulating top oxide layer, and a polysilicon control gate positioned on top of a crystalline silicon substrate. This particular structure of a silicon channel region, tunnel oxide, nitride, top oxide, and polysilicon control gate is often referred to as a SONOS device.
Similar to the floating gate device, the SONOS memory cell is programmed by inducing hot electron injection from the channel region to the nitride layer to create a non volatile negative charge within charge traps existing in the nitride layer. Again, hot electron injection can be achieved by applying a drain-to-source bias along with a high positive voltage on the control gate. The high voltage on the control gate inverts the channel region while the drain-to-source bias accelerates electrons towards the drain region. The accelerated electrons gain up to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV SiO
2
energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain region, those electrons which collide with the crystalline lattice are re-directed towards the SiO
2
under the influence of the control gate electric field and have sufficient energy to cross the barrier.
Because the nitride layer stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a charge storage region that is close to the drain region. More specifically, the accelerated electrons will reach sufficient energy to cross the energy barrier at a specific “hot point” distance between the source region and the drain region. In operation, the accelerated electrons reach sufficient energy within a very small deviation of the “hot point” and therefore the stored charge tends to be concentrated in the charge trapping layer around the “hot point”.
A problem associated with an extremely concentrated charge is that each electron is under a strong repulsive force from the other electrons. The high electric field created by these electrons subjects the surrounding dielectric material to field stress. Both factors can cause charge loss and misreading of the cell.
What is needed is a non-volatile dielectric memory cell structure and programming method that provides for increasing the size of the charge storage region and subsequently decreasing the charge concentration.
SUMMARY OF THE INVENTION
A first aspect of the present invention is to provide an array of non-volatile memory cells for storing a data pattern and reproducing the data pattern. The array comprises a plurality of memory cells arranged in a matrix with its rows defined by a plurality of parallel spaced apart word lines and its columns defined by a plurality of bit line diffusions within the substrate.
The array comprises a moderately doped p-type substrate. A plurality of spaced apart heavily doped n-type bit lines are formed through ion implantation into the p-type substrate to define channel regions there between. An insulating layer consisting of a tunnel insulator layer, a charge trapping (or storage) layer, and a top insulator layer, is formed on top of the substrate. A plurality of spaced apart polysilicon word lines are positioned on top of the insulator layer. Each of the word lines is perpendicular to the bit lines and a memory cell is formed at the intersection of each word line and each channel region.
Each channel comprises a moderately doped portion and a slightly more heavily doped portion. The moderately doped portion of the channel is adjacent to a first, or source, one of the bit lines and consists of moderately doped n-type material. The slightly more heavily doped portion of the channel is adjacent to a second, or drain, one of the bit lines and consist of a heavily doped n-type of material. The moderately doped portion and the slightly more heavily doped portion together comprise the entire channel.
The slightly more heavily doped portion facilitates kinetic energy gain of the electrons thereby enabling a portion of the electrons to gain sufficient energy to cross the 3.2 eV SiO
2
barrier at a point within the channel that is closer to the source region than the point at which such electrons would have gained sufficient energy without the heavier doping concentration. As such, the linear distribution across the channel length (e.g. distance between the source bit line and the drain bit line) at which electrons gain sufficient energy to cross the SiO
2
barrier is increased, but still confined to the slightly more heavily doped portion of the channel region.
An array control circuit is coupled to each bit line and each word line. The array control circuit provides a drain to source programming potential bias to draw electrons from the source bit line into the channel region and accelerate the electrons towards the drain bit line during programming of a memory cell.
The array control circuit also provides a word line programming potential to a selected one of the word lines to provide an electric filed thereby diverting the accelerated electrons from the channel region beneath the selected word line across the tunnel insulator film into the charge storage region. The electrons are diverted over a substantial portion of the channel length within the slightly more heavily doped channel region to decrease the trapped charge density and spread the trapped charge over a substantial portion of the channel length.
More specifically, the drain bit programming potential and the word line programming potential provide for approximately 0.01 percent of the electrons drawn from the source bit line diffusion to gain adequate kinetic energy to cross the energy barri
Li Yu
Liu Zhizheng
Randolph Mark W.
Advanced Micro Devices , Inc.
Nelms David
Nguyen Thinh T
Renner , Otto, Boisselle & Sklar, LLP
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