Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-11-25
2004-04-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06718528
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a latch-up verifying method and a latch-up verifying apparatus for verifying layout data of a semiconductor integrated circuit. More specifically, the present invention is directed to latch-up verifying method/apparatus capable of varying an over-sized region, depending upon structural conditions and also electric characteristics of semiconductor integrated circuits.
2. Description of the Related Art
Very recently, while semiconductor integrated circuits are manufactured in very fine manners, occurrence potentials of erroneous IC operations caused by a so-called “latch-up” phenomenon are increased. In a CMOS (complementary MOS) semiconductor integrated circuit, it is normally known that a “latch-up” phenomenon occurs. That is, while such CMOS semiconductor integrated circuits are manufactured in a very fine manner and in a high integration, parastic transistors are formed. Under such a circumstance, when such a phenomenon happens to occur that a base current along a forward direction may flow through any one of a PNP transistor and an NPN transistor, which constitute a CMOS semiconductor integrated circuit, both the PNP transistor and the NPN transistor are simultaneously turned ON to be therefore brought into a positive feedback condition. Thus, these ON states of the PNP/NPN transistors are not ceased unless supplying of electric power to these transistors is interrupted.
As one of effective solving items, there is a latch-up verifying method executed based upon layout data.
This sort of conventional latch-up verifying method is described in, for instance, Japanese Laid-open Patent Application No. Hei-7-130965 opened in 1995. Concretely speaking, this conventional latch-up verifying method is constituted by: at least a well region extracting step; a transistor region extracting step; a substrate contact region extracting step; an over-sizing executing step; and a latch-up verifying step. This conventional latch-up verifying method employs the distance between the substrate contact region and the transistor region as the verifying material.
Next, one conventional latch-up verifying method will now be explained.
FIG. 13
is a flow chart for describing this conventional latch-up verifying method. This conventional latch-up verifying method verifies as to whether or not a distance between a substrate contact region and a transistor region is equal to such a distance which can sufficiently avoid an occurrence of a so-called latch-up phenomenon in accordance with a preset over-sizing value. This over-sizing value is previously set based upon input layout data D
1
. As a result, latch-up verification data D
12
is obtained. In other words, this conventional latch-up verifying method is constituted by: a step S
1
for extracting a well region; a step S
2
for extracting a transistor region; a step S
3
for extracting a substrate contact region; a step S
16
for executing a so-called “over-sizing step”, namely for drawing a safe range from the substrate contact region by using a value set every process; and also a latch-up verifying step S
7
for verifying as to whether or not the transistor region is not deviated from, or is sticking out from the over-sized region, i.e., the safe range.
Next, operations of the above-explained latch-up verifying method with employment of the above-described steps will now be explained in detail.
At the first step S
1
, the well region is extracted based on the input layout data D
1
. Next, the transistor region is extracted based upon the input layout data DI at the step S
2
. At the subsequent step S
3
, the substrate contact region is extracted based on the input layout data D
1
. At the step S
16
, the safe range (namely, over-sized region) from the substrate contact region is drawn based upon the various data extracted from the step S
1
, the step S
2
, and the step S
3
, while employing a constant value set every process as over-sized data, and then the over-sizing step is executed. The latch-up verification defined at the step S
7
is executed. That is to say, the logic calculation is carried out between the safe range where the over-sizing step is executed at the step S
16
, namely the substrate contact region enlarged (over-sized) by the over-sizing step, and the transistor region extracted at the step S
2
. As a result, the transistor region existing outside the over-sizing region of the substrate contact region set in the above-explained over-sizing step is extracted. As a result of the extracting execution of this step S
7
, the latch-up verification resultant data D
12
is obtained.
However, this conventional latch-up verifying method owns the following problem. That is, since the over-sizing value is set to such a constant value with respect to each process, the latch-up verification cannot be executed in high precision.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described problem of the conventional latch-up verifying method, and therefore, has an object to provide a latch-up verifying method and a latch-up verifying apparatus, capable of executing latch-up verification in high precision.
To achieve the above-explained object, when latch-up verification for layout data is carried out, a well region, a transistor region, and a substrate contact region are extracted from the layout data. Thereafter, an over-sized region is set by (respectively) separately setting over-sizing values based upon the extracted information of the above-explained regions, and by executing an over-sizing step for the substrate contact region. Then, the latch-up verification can be executed in high precision by judging as to whether the transistor region is contained in this over-sized region.
A latch-up verifying method, according to a first aspect of the present invention, is featured by that a well region, a transistor region, and a substrate contact region are extracted from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and steps for separately setting over-sizing values are sequentially executed based upon the respective extracted information, whereby latch-up verification of the layout data is executed.
In accordance with the above-described arrangement, since the over-sized values are separately set based upon the respective extracted information of the well region, the transistor region, and the substrate contact region from the layout data of the semiconductor integrated circuit formed on the, semiconductor substrate, the judgement can be carried out by considering various conditions. As a result, the latch-up verification can be done in high precision. In other words, an occurring risk of such a latch-up phenomenon will largely depend upon the structural condition and the current capability (electric characteristic). The structural condition is defined from the positional relationship among the respective regions, for instance, the distance of the region from the well region; and further defined from the conductivity type of the semiconductor substrate, the carrier density, and the dimension of the contact region. As a result, since the over-sizing region is set by considering these conditions, the latch-up verification precision can be largely increased.
Also, a latch-up verifying method, according to a second aspect of the present invention, is featured by such a latch-up verifying method of the first aspect, wherein: the latch-up verifying method is comprised of: a step for forming a database used to store an over-sizing value; a first extraction step for extracting a well region from the layout data; a second extraction step for extracting a transistor region from the layout data; a third extraction step for extracting a substrate contact region from the layout data; an over-sizing determining step for determining an over-sizing value based upon the extracted information obtained from the first extraction step to the third extraction step with reference to the over-sizing valu
Kimura Shin-ichi
Tsujikawa Hiroyuki
Matsushita Electric - Industrial Co., Ltd.
Pearne & Gordon LLP
Siek Vuthe
LandOfFree
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