Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-31
2004-03-09
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S339000, C257S342000
Reexamination Certificate
active
06703664
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a power field effect transistor (FET) device.
DESCRIPTION OF THE RELATED ART
Known power FET devices comprise a semiconductor wafer substrate upon which a series of structures is defined, each structure forming a single FET element arranged such that all of the individual FET elements are connected in parallel. The semiconductor wafer defines first and second surfaces, a gate electrode extends over the first surface of the substrate, and a drain electrode extends over the second surface of the substrate. The known devices can generally be categorised as either of “cellular” design or “stripe” design.
In cellular designs, the gate electrode defines a regular army of rows and columns of apertures, each aperture defining the location of one FET element. During fabrication, an FET body region of a first conductivity type is formed through each of the gate apertures such that an array of body regions is formed in the first surface of the substrate, each body region being located beneath a respective gate electrode aperture and extending laterally under the edges of the gate electrode defining that aperture. A source region of a second conductivity type is then formed in each of the body regions through the apertures in the gate electrode, the source regions extending laterally beneath the aperture edges into the body region. The source regions do not extend to the peripheral edges of the body regions and therefore channel regions are defined in the body regions around the source regions and beneath the gate electrode. The gate electrode is electrically isolated from the substrate by a layer of gate oxide.
Current flow through the device is controlled by controlling a voltage applied between the gate electrode and a source electrode which contacts each of the source regions through the apertures in the gate electrode. Current passes vertically through The substrate between the source and drain electrodes via the channel regions which extend around the circumference of each of the gate electrode apertures.
One known cellular design is described in U.S. Pat. No. 5,008,725. In that design, a plurality of simple hexagonal-shaped body regions, each containing a source region, are closely packed on one surface of a semiconductor body. Gate electrodes extend between adjacent sources and control conduction from the source electrode through the channels and then to a drain electrode on the opposite surface of the semiconductor body. Each source overlies a p-type body region, the body regions of adjacent FET elements being separated by n-type material through which current flows between the source and drain after passing laterally through the channels beneath the gate electrodes. The use of a basic hexagonal structure makes it possible to ensure a constant spacing between adjacent edges of the sources and thereby enables a large number of small hexagonal source elements to be formed in a given area of semiconductor body.
In “stripe” designs, rather than relying upon an array of rows and columns of cells, a single column of elongate structures is formed, each elongate structure defining one “stripe”. The gate electrode defines a column of elongate slot-like apertures, each aperture defining the location of one FET element Body and source regions are forced through each of the apertures and extend laterally beneath the edges of the apertures.
It is known that the DC on resistance of FET's is a function of the total peripheral source region edge length, which in turn is a function of the total length of the gate electrode aperture edge. This length can be made greater in cellular designs than in stripe designs, and therefore cellular designs have been preferred in applications in which DC on resistance is of primary importance. It is also known however that the AC switching performance of FET's is a function of the gate/drain overlap area (the area beneath the gate electrode not occupied by body region). This area is greater in cellular designs than in stripe designs, and therefore stripe designs have been preferred in some applications in which AC switching performance is of primary importance.
U.S. Pat. No. 5,521,410 describes an alternative design which seeks to achieve a relatively long gate electrode aperture edge by using complex elongate source region shapes. In that arrangement, square openings are formed in a gate electrode, and pairs of the square openings are connected by slits. With such an arrangement, although only a relatively small number of source regions can be provided in a given substrate area, the slits provide a relatively long source region edge. The body region of each basic double opening and slit arrangement extends by the same distance laterally relative to all of the structure and as a result the distance between adjacent body regions can be vent small (in one of the illustrated examples only 0.04 micrometers). In a practical device, given fabrication tolerances and errors, adjacent body regions might contact each other, but only to a limited and accidental extent.
It is an object of the present invention to provide an improved power FET device which may have a relatively large source region edge length per unit area and a relatively small gate/drain overlap area.
SUMMARY
According to the present invention, there is provided a power FET device comprising a semiconductor wafer substrate defining first and second surfaces, a gate electrode extending over the first surface of the substrate, the gate electrode defining a regular array of apertures and being insulated from the substrate, a drain electrode extending over the second surface of the substrate, an FET body region of a first conductivity type formed in the first surface of the substrate beneath each gate electrode aperture and extending a first predetermined lateral distance from edges of the gate electrode defining the aperture, an FET source region of a second conductivity type formed within the body region beneath each gate electrode aperture, each FET source region extending a second predetermined lateral distance from the edges of the gate electrode defining the aperture, a source electrode interconnecting source contacts located beneath each of the gate electrode apertures, and an FET channel region defined around the periphery of each of the source regions beneath the gate electrode, each gate electrode aperture being separated from at least one adjacent gate electrode aperture by a strip of gate electrode the width of which varies along the length of the strip between a maximum which is substantially greater than twice the first distance and a minimum which is substantially greater than twice the second distance and substantially less than twice the first distance, whereby a single body structure extends continuously between the said adjacent gate electrode apertures at each position of minimum inter-aperture width due to lateral merging of the body regions at each such position.
The invention also provides a method for forming a power FET device, wherein a gate electrode is formed on a first surface of the semiconductor wafer substrate, the gate electrode defining a regular array of apertures and being insulated from the substrate, a drain electrode is formed on a second surface of the substrate, an FET body region of a first conductivity type is formed in the first surface of the substrate beneath each gate electrode aperture so as to extend beneath edges of the gate electrode apertures, an FET source region of a second conductivity type is formed within the body region beneath each gate electrode aperture so as to extend beneath the edges of the gate electrode apertures, and a source electrode is formed to interconnect source contacts located beneath each of the gate electrode apertures, an FET channel region being defined in the body region around the periphery of each of the source regions beneath the gate electrode, the edges of the gate electrodes being shaped and positioned such that each gate electrode aperture is separated from
Loke Steven
Morrison & Foerster / LLP
Zetex PLC
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