Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2002-04-16
2004-04-27
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
C365S189070, C365S189090, C365S226000
Reexamination Certificate
active
06728141
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit for timing dynamic reading of a memory cell with control of the integration time.
2. Description of the Related Art
As is known, the need for nonvolatile memories having increasingly larger densities has led to manufacturing multi-level memories wherein the information, stored as charge quantity in a floating-gate region, is encoded by fractioning the entrapped charge. In this way, the characteristic of a multilevel flash cell is described by a number of curves representing the pattern of the drain current Ids as a function of the gate voltage Vgs, each curve being associated to a different logic value. For examples
FIG. 1
shows the characteristic of a four-level (2-bit) flash cell which stores the bits “11”, “10”,“01”, and “00”, corresponding to threshold voltages Vt
1
, Vt
2
, Vt
3
and Vt
4
.
Reading of multi-level cells is carried out evaluating the current or the voltage.
Current reading is based on comparing the current flowing in a cell at a preset gate voltage Vgs and the current flowing in a reference cell, the characteristic of which is intermediate between the distributions of the programmed cells, as shown in FIG.
2
. The comparison is made after a current-to-voltage conversion, both of the current of the cell and of the reference current.
Current reading has a number of problems, the main ones depend on parasitic resistances, such as source and drain-contact resistance of the cell, resistance of the metal connections, and resistance caused by the pass transistors of the column decoder.
As a whole, the result is a reduction in current dynamics. Consequently, the comparator that compares the voltages after current-to-voltage conversion must have a greater sensitivity. In addition, the actual characteristics differ with respect to the ideal ones, as shown in FIG.
3
. Due to such non-idealities, current reading of multilevel memory cells having more than two bits per cell is difficult, because it is required to distinguish extremely close current levels from one another.
To overcome the above problems, U.S. Pat. No. 6,034,888, in the name of the present Applicant, proposes a voltage reading method using a closed-loop circuit (see FIG.
4
). In this circuit, the current of the cell to be read is compared with a reference current, and the gate voltage of the cell is modulated until reaching the equilibrium of the system. Thereby, the gate voltage of the cell reaches a value that can be defined as the threshold value of the cell.
However, also this solution is not free from problems, due to the need for an A/D converter able to read the voltage on the gate terminal of the cell, and to the constraint of not being able to read more than one cell at a time, since the row is in common to more than one cell and cannot assume different voltage values.
The solutions devised for solving the above problems moreover involve other disadvantages (increase in read time, greater area) and in any case call for the capacity to discriminate very small currents. On the other hand, the new technologies, involving a reduction in the cell dimensions, lead in turn to a reduction in the cell current, even though solutions are known for reducing the parasitic effects that determine the losses of linearity.
More recently, a dynamic reading of memory cells has been proposed, as described in European Patent Application N. 01830017.8 of Jan. 15, 2001, in the name of the present Applicant. Such proposal, which is based on time integration of the electric charge supplied to a memory cell to be read through a charging step or a discharging step of a capacitive element, will be hereinafter discussed, with reference to
FIGS. 5 and 6
.
In
FIG. 5
, a memory cell is represented by a current source
10
, which is connected between a ground line or connection—hereinafter referred to as ground line
19
—and a charge-transfer node
11
. The current source
10
has a control node
10
a
receiving a first control signal s and absorbs a constant current I directed towards the ground line
19
, when enabled by the first control signal s. The charge-transfer node
11
is connected to a reading circuit
20
comprising a decoupling stage
21
, a charge-regeneration capacitor
22
having a capacitance Ca, and an integration capacitor
23
having a capacitance Cb.
In detail, the decoupling stage
21
, formed by a circuit known as “cascode”, comprises an inverting element, here an inverter
24
, having an input connected to the charge-transfer node
11
and an output connected to the gate terminal of a cascode transistor
25
, of NMOS type. The cascode transistor
25
moreover has a source terminal connected to the charge-transfer node
11
and a drain terminal connected to the drain terminal of a pass transistor
27
, of NMOS type. The pass transistor
27
has a gate terminal receiving a second control signal Vp and a drain terminal connected to a charge-integration node
28
.
The charge-regeneration capacitor
22
has a first terminal
22
a
connected to the charge-integration node
28
and a second terminal
22
b
connected to the ground line
19
. The charge-integration node
28
is connected to the drain terminal of a charge transistor
29
, of PMOS type. The charge transistor
29
has a source terminal connected to a biasing line
30
set at a bias voltage Vpcx and a gate terminal receiving a charge-enabling signal en. The bias voltage Vpcx can be either a standard supply voltage (e.g. of 3 V) or a boosted voltage (e.g,. of 6 V) provided by a boosting device of a known type and not shown herein.
Finally, the charge-integration node
28
forms the output of the reading circuit
20
, and generates a voltage Va proportional, as will be explained hereinafter, to the current I flowing in the current source
10
. A voltage Vb is present on the charge-transfer node
11
.
Operation of the circuit of
FIG. 5
is the following (see also FIGS.
6
A-E).
Initially, the voltages Va and Vb on the charge-integration node
28
and on the charge-transfer node
11
are low. The first control signal s keeps the current source
10
off. In addition, the charge-enabling signal en is low and keeps the charge transistor
29
on. The second control signal Vp is high and keeps the pass transistor
27
on. In this condition, the output of the inverter
24
is high, and the cascode transistor
25
is on and enables charging of the integration capacitor
23
up to the threshold voltage of the inverter
24
. As soon as the voltage Vb on the charge-transfer node
11
has reached the triggering voltage of the inverter
24
, the latter switches and turns off the cascode transistor
25
, which interrupts charging of the integration capacitor
23
. In addition, the charge-regeneration capacitor
22
charges up to the bias voltage (i.e., until Va=Vpcx).
In steady-state conditions, at the end of charging, the following relations apply:
V
ai
=Vpcx
Q
ai
=C
a
V
ai
=C
a
Vpcx
Q
bi
=C
b
V
bi
where V
ai
is the value of the voltage V
a
at the end of the charging step, Q
ai
is the charge stored in the charge-regeneration capacitor
22
, V
bi
is the value of the voltage V
b
at the end of the charging step, and Q
bi
is the charge stored in the integration capacitor
23
.
At the instant t
1
, the charge-enabling signal en switches to the high state (Vpcx) and turns off the charge transistor
29
(in this way isolating the charge-regeneration capacitor
22
from the supply line
30
). Next (instant t
2
), the second control signal Vp switches to low and turns off the pass transistor
27
(thereby isolating the charge-transfer node
11
and the charge-integration node
28
). Finally (instant t
3
), the first control signal s switches and turns on the current source
10
, which, to a first approximation, goes to a steady-state condition in a negligibly small time, so that the integration capacitor
23
will not be affected by current transients.
Consequently, the integration capacitor
23
discharges linear
Campardo Giovanni
Micheloni Rino
Iannucci Robert
Jorgenson Lisa K.
Nguyen Viet Q.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
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