Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-01-18
2004-04-20
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S048000
Reexamination Certificate
active
06724030
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to determining parameters of a trench semiconductor device.
2. Discussion of Related Art
In vertical trench Dynamic Random Access Memory (DRAM) devices, the DRAM is built into sidewalls of storage trenches. In trench DRAM technology the source side of the array device is floating and connected to a storage capacitor. In order to determine the parameters of such a device, the source needs to be accessed.
Accessing the back-side or source side of a device to extract the device parameters can be difficult. Typically, devices are measured in a back-to-back mode where the source side of each device is wired to the silicon (Si) surface by a second device. However, it can be difficult to determine device parameters from a single device in such an arrangement.
According to another approach, the trench geometry is altered, where the trench functions as a wire connecting the source to the front of the die. However, in the implementation of this approach, several levels of a macro design are modified wherein the macro design deviates drastically from the actual product design. For example, macro designs at the vertical trench level may be altered such that the source can be wired laterally to the side and up to the Si surface. Thus, the periodic arrangement of vertical trench may be interrupted. Further, the patterning of the Si substrate, or active area, may be altered. These alterations can influence the structure and surroundings of the array device. Thus, device parameters recovered using this approach may fail to accurately model the product design.
Therefore, a need exists for a system and method of recovering device parameters without substantially modifying the design of a test device from that of the product design.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a method is provided for forming a back-side contact for a vertical trench device. The method comprises grinding a backside of a semiconductor substrate, milling a trench in the backside of the semiconductor substrate, wherein a vertical trench fill is exposed, and depositing a conductive material, wherein the conductive material shorts the vertical trench fill to a buried plate.
The conductive material is a back-side electrode.
Grinding the back-side of the semiconductor substrate further comprises grinding a dimple beneath a portion of the vertical trench device, wherein the trench is milled in the bottom portion of the dimple. The depth of the silicon removed by the step of grinding is within the buried plate.
The conductive material is selected for a low contact resistance with Silica. The conductive material is selected from the group consisting of platinum and tungsten.
Depositing a conductive material further comprises depositing the conductive material in-situ by a focused ion beam method. Depositing a conductive material further comprises sputtering the conductive material over the bottom of the semiconductor substrate.
According to another embodiment of the present invention, a method is provided for connecting a floating source of a trench device to a back-side contact for the trench device. The method comprises grinding a back-side of a semiconductor substrate, milling a trench in the back-side of the semiconductor substrate, wherein a vertical trench fill is exposed, and depositing a back-side electrode in-situ by focused ion beam, wherein the conductive material shorts the vertical trench fill to a buried plate.
Grinding the back-side of the semiconductor substrate further comprises grinding a dimple beneath a portion of the trench device, wherein the trench is milled in the bottom portion of the dimple. The depth of the silicon removed by the step of grinding is within the buried plate.
The conductive material is selected for a low contact resistance with Silica. The conductive material is selected from the group consisting of platinum and tungsten.
According to an embodiment of the present invention, a memory device is provided having an accessible source such that device parameters can be determined. The device comprises a dimple ground into a back-side of a semiconductor substrate of the device, a trench milled from the bottom portion of the dimple exposing a portion of a vertical trench fill, and a conductive material connecting the vertical trench fill and a source of the device.
The trench is milled into a portion of the vertical trench fill.
The conductive material is a back-side electrode. The conductive material is a layer covering a portion of the backside of the semiconductor substrate.
A macro design of the memory device is substantially similar to a product line macro design. The memory device dimensions are substantially the same as those of the product line macro design.
REFERENCES:
patent: 5990562 (1999-11-01), Vallett
patent: 6078057 (2000-06-01), Vallett
patent: 6277659 (2001-08-01), Goruganthu et al.
patent: 6545490 (2003-04-01), Bruce
patent: 6599778 (2003-07-01), Pogge et al.
patent: 2001/0006233 (2001-07-01), Vallett
patent: 2003/0111733 (2003-06-01), Pogge et al.
Flynn Nathan J.
Infineon Technologies North American Corp.
Mondt Johannes
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