Time-out counter for multiple transaction bus system bus bridge

Details Time-out counter for multiple transaction bus system bus bridge Time-out counter for multiple transaction bus system bus bridge

2001-08-17

2004-07-06

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S306000, C710S315000, C710S056000

Reexamination Certificate

active

06760802

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is data transfer and data bus systems within computer systems.
BACKGROUND OF THE INVENTION
As computer systems have grown more complex, it has become common to employ multiple processors and a wide variety of peripheral devices to transfer data within a chip and from the chip to external devices and vice versa. Such systems almost always have a multiple set of busses separating, for convenience and performance reasons, the communication between similar devices. Multiple bus systems must provide bus controllers to allow for coherent and collision-free communication between separate buses. Micro-controllers are used for this purpose and they provide bus arbitration which determines, at a given time, which device has control of the bus in question.
A prominent standard bus system has emerged for high performance micro-controller designs. The ‘Advanced Micro-controller Bus Architecture System’ AMBA has been defined by Advanced RISC Machines (ARM) Ltd. (Cambridge, U.K.) and is described in U.S. Pat. No. 5,740,461, dated Apr. 14, 1998. Computer systems of a CISC variety are complex instruction set computers and have total backward compatibility requirements over all versions. RISC (reduced instruction set computer) systems, by contrast, are designed to have simple instruction sets and maximized efficiency of operation. Complex operations are accomplished in RISC machines as well, but they are achieved by using combinations of simple instructions. The RISC machines of ARM Ltd. forming the AMBA architecture are of primary interest here.
The standard AMBA has two main busses, a high performance AHB bus and a peripheral bus APB of more moderate performance. The AHB bus is the main memory bus and contains RAM and an external memory controller. In this basic system definition, if a high performance peripheral is required that will transfer large amounts of data, this peripheral is also placed on the high performance AHB bus. This decreases system performance, however, because the central processor unit (CPU) cannot have access to memory when the peripheral has control of the bus.
Advanced RISC Machines Ltd (ARM) has proposed an efficient arbitration scheme and split transfers to allow the CPU and the high performance peripheral to share bus time of the single AHB bus. ARM has also proposed use of a second bus for isolation and using a single arbiter. This proposal still allows only one transaction to progress at a given time period.
SUMMARY OF THE INVENTION
In a multiple transaction AHB bus system (MTAHB), if a master on one bus needs to read data from a slave on another bus, it must first arbitrate and win control on the primary AHB bus (the memory bus AHB in the MTAHB system). Then it must wait for arbitration and control of the secondary AHB bus (the high performance data transfer bus HTB in the MTAHB system). During this time, the primary AHB bus is held and no useful work can be done.
The time-out counter of this invention provides a capability in the AHB-to-HTB bus bridge for an AHB bus master to time-out if it is not given control of the bus in a certain time period. This would generally occur if the time of arbitration on the secondary HTB bus is excessive. The time-out counter is programmable up to 16-bits in the preferred embodiment. This allows the software flexibility in choosing the length of the time-out period.
This time-out feature is an addition to the concept of the original AHB bus and is useful if the manner of arbitration used would allow the bus master to have total control of the AHB bus. This shows itself in the AHB-HTB bus bridge when the AHB bus master requests a read, but the HTB peripheral may be in the process of a long data transfer and cannot be interrupted. The AHB peripheral can then time-out and begin or resume another task.
The time-out counter of this invention interacts with the rest of the system by generating an interrupt request when its content reaches hexadecimal ‘0000’. The central processing unit (CPU) then handles the interrupt and can switch tasks or perform some other function. The time-out counter interacts with no other modules outside the domain of the AHB-to-HTB bridge.


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