Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-02-08
2004-07-27
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S056000, C710S109000
Reexamination Certificate
active
06769078
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to computer bus architecture. More specifically, the present invention relates to Inter Integrated Circuit (I
2
C) buses.
2. Description of Related Art
Many similarities exist between seemingly unrelated designs in consumer, industrial and telecommunication electronics. Examples of similarities include intelligent control, general-purpose circuits (i.e. LCD drivers, I/O ports, RAM) and application-oriented circuits. The Philips Inter Integrated Circuit (I
2
C) bus is a bi-directional two-wire serial bus designed to exploit these similarities.
Devices on the I
2
C bus are accessed by individual addresses, 00-FF (even addresses for Writes, odd addresses for reads). The I
2
C architecture can be used for a variety of functions. One example is Vital Product Data (VPD). Each component in the system contains a small Electrically Erasable Programmable Read Only Memory (EEPROM) (typically 256 bytes) which contains the VPD information such as serial numbers, part numbers, and EC revision level.
I
2
C busses can connect a number of devices simultaneously to the same pair of bus wires. However, a problem results when one of the devices malfunctions and pulls a bus signal (clock or data) low the bus will not operate and it is very difficult to determine which of the numerous devices connected to the I
2
C bus is responsible. A similar problem occurs when one of the bus conductors becomes shorted to a low impedance source, such as, for example, ground.
Therefore, an method, computer program product, system, and improved I
2
C bus for isolating the device that has malfunctioned resulting in the bus ceasing to operate would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a method, system and computer program product for determining the source of a fault within a bus, such as, for example, an inter integrated circuit (I2C) bus. In one embodiment a bus driver monitors the bus for faults. If a fault occurs on the bus, the bus driver resets each switch on the bus and then turns on the first switch connected to the bus driver. If the fault is encountered after turning on the first switch, then it is determined that the fault was caused by either the first switch, a device connected to the bus as a result of turning on the first switch, or one of the bus connectors just switched on as a result of turning on the first switch. If the fault is not encountered, the next switch is turned on and the process is repeated until the fault is encountered. The fault when encountered will be caused by either the most recently turned on switch or a device or bus connectors switched in by the turning on of the last switch. Thus, the fault can be isolated to a few devices, switches, or bus connections rather than the large number of potential devices, switches, or bus connections that could have potential caused the fault.
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patent: 6324596 (2001-11-01), Houg
patent: 6590755 (2003-07-01), Behr et al.
Barenys Michael Anton
Faust Robert Allan
Goodwin Joel Gerald
Beausoliel Robert
International Business Machines - Corporation
McBurney Mark E.
McCarthy Christopher
Yee Duke W.
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