Stacked chip package with enhanced thermal conductivity

Details Stacked chip package with enhanced thermal conductivity Stacked chip package with enhanced thermal conductivity

2002-09-03

2004-03-30

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S680000, C257S777000

Reexamination Certificate

active

06713856

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit (IC) chip package, and more particularly to a stacked chip package with enhanced thermal dissipation.
2. Description of the Prior Art
U.S. Pat. No. 6,387,728 discloses a conventional stacked chip package
1
, as shown in
FIG. 1
, which comprises a first chip
3
and a second chip
6
stacked each other. The first chip
3
is attached onto the upper surface of a substrate
2
. An adhesive layer
5
is interposed between the chips
3
,
6
. The chips
3
,
6
are respectively connected to the upper surface of the substrate
2
through bonding wires
4
,
7
. An encapsulant
8
covers the chips
3
,
6
, the bonding wires
4
,
7
and a portion of the upper surface of the substrate
2
.
The stacked chip package includes two or more chips disposed on a substrate. It saves space efficiently. But the heat generated by the chips is hard to dissipate. The high temperature may disable the chips. Besides, because the bonding wires
4
are not protected when the second chip
6
is disposed on the adhesive layer
5
, the second chip
6
may touch the bonding wires
4
and destroy them. It will draw down the yield dramatically.
SUMMARY OF THE INVENTION
It is the primary objective of the present invention to provide a stacked chip package having superior heat-dissipating ability.
It is another objective of the present invention to provide a stacked chip package that can enhance the yield thereof.
It is still another objective of the present invention to provide a stacked chip package saving space more efficiently thereof.
In keeping with the principle of the present invention, the foregoing objectives of the present invention are attained by the stacked chip package comprising a substrate, a first chip, a thermally and electrically conductive adhesive layer, a thermally and electrically conductive planar member, a first encapsulant, a second chip, a second encapsulant, and a plurality of solder balls. The substrate has an upper surface, a lower surface and a through hole. The first chip has an active side and an inactive side and is received in the through hole of the substrate in such a way that the active side of the first chip and the upper surface of the substrate face to a same direction. The active side of the first chip is electrically connected to the upper surface of the substrate through first bonding wires. The adhesive layer is disposed on the inactive side of the first chip and the lower surface of the substrate in a completely enclosing way around the through hole. The planar member has an upper surface and a lower surface and is attached to the adhesive layer with the upper surface thereof. The first encapsulant is disposed on the active side of the first chip. The second chip has an active side and an inactive side and is attached to the first encapsulant with the inactive side thereof. The active side of the second chip is electrically connected to the upper surface of the substrate through second bonding wires. The second encapsulant is disposed on the upper surface of the substrate and covers the first chip, the first bonding wires, the first encapsulant, the second chip and the second bonding wires. The second encapsulant also fills the through hole. The solder balls are electrically connected to the lower surface of the substrate.


REFERENCES:
patent: 5502289 (1996-03-01), Takiar et al.
patent: 5583378 (1996-12-01), Marrs et al.
patent: 5650593 (1997-07-01), McMillan et al.
patent: 6387728 (2002-05-01), Pai et al.
patent: 2002/0008316 (2002-01-01), Miyazaki
patent: 2003/0042615 (2003-03-01), Jiang et al.
Wolf et al., Silicon Processing for the VLSI Era, 2000, vol. 1, 851-852.

Affiliated with

Also associated with

Rating

Stacked chip package with enhanced thermal conductivity does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stacked chip package with enhanced thermal conductivity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked chip package with enhanced thermal conductivity will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3225557