Data processing: measuring – calibrating – or testing – Measurement system – Temperature measuring system
Reexamination Certificate
2002-02-14
2004-03-09
Shah, Kamini (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Temperature measuring system
C702S117000, C327S512000, C324S760020
Reexamination Certificate
active
06704680
ABSTRACT:
BACKGROUND OF INVENTION
To increase processor performance, clock frequencies used by microprocessors, often referred to as “CPUs,” have increased. Also, as the number of circuits that can be used in a CPU has increased, the number of parallel operations has risen. Examples of efforts to create more parallel operations include increased pipeline depth and an increase in the number of functional units in super-scalar and very-long-instruction-word architectures. As processor performance continues to increase, the result has been a larger number of circuits switching at faster rates. Thus, from a design perspective, important considerations such as power, switching noise, and signal integrity must be taken into account.
Higher frequencies and data throughput cause a processor to consume increased power and run at increased temperatures. Extreme temperatures can slow the speed of transistors that may cause some CPU activities to be incomplete at the end of a cycle. The effect may lead to loss of data in a CPU or incorrect results; therefore, on-chip temperature sensors are employed for monitoring. The availability of temperature information allows the CPU to reduce the number of activities and/or slow the operating frequency. If scaling the number of activities does not alleviate the condition, a standby or power down mode may be entered to protect the CPU. Accurate temperature information is important to prevent over heating or unnecessary reduction in CPU activities.
Higher frequencies for an increased number of circuits also increases switching noise on the power supply. The switching noise may have a local or global effect. Circuits that create large amounts of noise may be relatively isolated; however, they may also affect other circuits, possibly involving very complex interactions between the noise generation and the function of affected circuits. If the components responsible for carrying out specific operations do not receive adequate power in a timely manner, computer system performance is susceptible to degradation. For example, on-chip temperature sensor accuracy varies with power supply noise. Thus, providing power to the components in a computer system in a sufficient and timely manner has become an issue of significant importance.
Often, power supplied to a computer system component varies due to switching by active circuits, which in turn, affects the integrity of the component's output. Typically, this power variation results from parasitics between a power supply for the component and the component itself. These parasitics may lead to the component not receiving power (via current) at the exact time it is required. One approach used by designers to combat this performance-inhibiting behavior is introducing decoupling capacitance to a particular circuit by positioning one or more decoupling capacitors close to the component. These decoupling capacitors store charge from the power supply and distribute the charge to the component when needed. For example, if power received by a component from a power supply has noise, one or more decoupling capacitors will distribute charge to the component to ensure that the component is not affected by the power variation on the power supply. In essence, a decoupling capacitor acts as a local power supply for one or more specific components in a computer system.
For a circuit designer to appropriately design an on-chip temperature sensor, a good understanding of the behavior of the system is required.
FIG. 1
shows a section of a typical power supply network (
100
) of a computer system. The power supply network (
100
) may be representative of a single integrated circuit, or “chip”, or equally an entire computer system comprising multiple integrated circuits. The power supply network (
100
) has a power supply (
112
) that provides power through a power supply line (
114
) and a ground line (
116
) to an impedance network Z
1
(
118
). The impedance network is a collection of parasitic elements that result from inherent resistance, capacitance, and/or inductance of physical connections. A power supply line (
122
,
123
) and a ground line (
124
,
125
) supply power to a circuit A (
120
) and circuit B (
126
), respectively. Power supply line (
123
) and ground line (
125
) also supply power to circuit C (
130
) through another impedance network Z
2
(
128
) and additional impedance networks and circuits, such as impedance network Z
n
(
132
) and circuit N (
134
). The impedance network and connected circuits may be modeled so that the designer, using a simulator, can better understand the behavior of how the circuits interact and interdependencies that exist.
Still referring to
FIG. 1
, circuit A (
120
), circuit B (
126
), circuit C (
130
), and circuit N (
134
) may be analog or digital circuits. Also, circuit A (
120
), circuit B (
126
), circuit C (
130
), and circuit N (
134
) may generate and/or be susceptible to power supply noise. For example, circuit C (
130
) may generate a large amount of power supply noise that affects the operation of both circuit B (
126
) and circuit N (
134
). The designer, in optimizing the performance of circuit B (
126
) and circuit N (
134
), requires an understanding of the characteristics of the power supply noise. By understanding the characteristics of the power supply noise, the designer has a foundation on which to use a variety of design techniques to minimize the amount of power supply noise. One such technique, as discussed above, is the addition of decoupling capacitance. For example, decoupling capacitor C
N
(
136
) located between a power supply line (
133
) and a ground line (
135
) may be added to reduce power supply noise. The amount of capacitance, due to the large amount needed for some designs, is an issue of significant importance.
SUMMARY OF INVENTION
According to one aspect of the present invention, a method for optimizing a decoupling capacitance for an on-chip temperature sensor comprises inputting a representative power supply waveform having noise to a simulation of the on-chip temperature sensor, determining a difference between a temperature representative input and a temperature dependent output of the on-chip temperature sensor, adjusting an amount of the decoupling capacitance, and repeating the inputting and determining the difference until the difference falls below a pre-selected value.
According to another aspect of the present invention, a computer system for optimizing a decoupling capacitance for an on-chip temperature sensor, comprises a processor, a memory, and software instructions stored in the memory adapted to cause the computer system to input a representative power supply waveform having noise to a simulation of the on-chip temperature sensor, determine a difference between a temperature representative input and a temperature dependent output of the on-chip temperature sensor, adjust an amount of the decoupling capacitance, and repeat the input and determine the difference until the difference falls below a pre-selected value.
According to another aspect of the present invention, a computer-readable medium having recorded thereon instructions executable by a processor, the instructions adapted to input a representative power supply waveform having noise to a simulation of an on-chip temperature sensor, determine a difference between a temperature representative input and a temperature dependent output of the on-chip temperature sensor, adjust an amount of a decoupling capacitance, and repeat the input and determine the difference until the difference falls below a pre-selected value.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.
REFERENCES:
patent: 6055489 (2000-04-01), Beatty et al.
patent: 6337595 (2002-01-01), Hsu et al.
patent: 6396137 (2002-05-01), Klughart
patent: 6476663 (2002-11-01), Gauthier et al.
patent: 6483341 (2002-11-01), Gauthier et al.
patent: 6566900 (2003-05-01), Amick et al.
Amick Brian
Gauthier Claude
Liu Dean
Trivedi Pradeep
Rosenthal & Osha L.L.P.
Shah Kamini
Sun Microsystems Inc.
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