Static random access memory with symmetric...

Details Static random access memory with symmetric... Static random access memory with symmetric...

2002-09-10

2004-03-16

Tran, Michael (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S207000

Reexamination Certificate

active

06707708

ABSTRACT:

FIELD
Embodiments of the present invention relate to circuits, and more particularly, to static random access memory circuits.
BACKGROUND
SRAM (Static Random Access Memory) is a memory technology that finds important applications in high speed caches or register files. Such high speed memory is often integrated on a die with a microprocessor core, and may be used to store instructions, as well as data used and generated by a microprocessor. For example, a portion of a computer system is abstracted at a high level in FIG.
1
. Microprocessor
102
comprises cache
104
and register files
106
, which in turn comprises SRAM memory. Cache
104
may be part of a memory hierarchy to store instructions and data, where system memory
108
is part of the memory hierarchy. Communication between microprocessor
102
with memory
108
is facilitated by memory controller (or chipset)
110
, which also facilitates in communicating with peripheral components
112
. Microprocessor communicates directly with memory controller
110
via bus or point-to-point interconnect
114
.
As process technology scales to smaller and smaller dimensions, subthreshold leakage current in transistors may present problems. For example, reading a memory cell in SRAM usually relies upon the development of a differential voltage on a pair of bit lines, where the differential voltage is indicative of the stored information bit. There are many other memory cells sharing the same pair of bit lines. During a read operation, the subthreshold leakage current in the cells not being read may cause an incorrect differential voltage to be sensed on the bit lines.
The above example is illustrated in FIG.
2
. Memory cell
202
comprising cross-coupled inverters
204
and
206
is being read by asserting word line
208
HIGH (e.g., V
CC
). Memory cell
202
provides a differential voltage on bit lines
210
and
212
. For simplicity, only two other memory cells, illustrated in dashed lines, are shown sharing bit lines
210
and
212
, but in practice there will be many more such memory cells. (Assume in the discussion that follows regarding
FIG. 2
that all other memory cells sharing the bit lines have the same states as those shown in dashed lines.) Memory cell
202
has a state in which node
214
is LOW (e.g., V
SS
) and node
216
is HIGH. A worst case scenario is illustrated in which those memory cells not being read are such that they store data bits in which nodes
214
a
and
214
b
are HIGH and nodes
216
a
and
216
b
are LOW. With word line
208
asserted HIGH, access nMOSFETs (n-Metal Oxide Semiconductor Field Effect Transistor)
218
and
220
are ON. With both bit lines pre-charged HIGH, bit line
210
will ideally discharge and bit line
212
will ideally maintain its HIGH state so that sense amplifier
222
will sense the correct differential voltage. However, although access nMOSFETs
218
a
,
218
b
,
220
a
, and
220
b
are OFF, there will be leakage current through them. This leakage current works against memory cell
202
discharging bit line
210
, and works against memory cell
202
keeping bit line
212
HIGH. As a result, a read operation is more susceptible to noise on the bit lines causing sense amplifier
222
to provide an incorrect result.


REFERENCES:
patent: 4914629 (1990-04-01), Blake et al.
patent: 5426614 (1995-06-01), Harward
patent: 6262911 (2001-07-01), Braceras et al.
Agawa, et al.,A Bitline Leakage Compensation Scheme for Low-Voltage SRAMs, IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001.
Alvandpour et al., U.S. patent application entitled:Current Leakage Reduction for Loaded Bit-Lines in On-Chip Memory Structures, application No. 09/896,348, filed Jun. 28, 2001.

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