Miniature device with increased insulative spacing and...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

Reexamination Certificate

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C257S355000, C257S358000, C257S691000, C257S750000, C257S758000

Reexamination Certificate

active

06759734

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to miniature devices and more particularly to miniature devices having layered structures.
BACKGROUND
Deep reactive ion etched electrostatic actuators have great utility for use in systems, particularly systems having optical components. These actuators have the potential for relatively large actuation forces due to the large surface area of the actuation plates. The force on such an actuator approximates the square of the applied voltage, regardless of the actuator capacitive plate arrangement. The actuator structure of such device must be able to resist voltage breakdown, which requires effective electrical insulation between the drive electrodes and the substrate material.
U.S. Pat. No. 5,998,906, the entire content of which is incorporated herein by this reference, describes use of deep reactive ion etching (DRIE) to produce electrostatic actuators. DRIE is also described in a paper entitled, “Silicon Fusion Bonding And Deep Reactive Ion Etching; A New Technology For Microstructures” by Klassen, Peterson, Noworolski, Logan, Maluf, Brown, Storment, McCully, and Kovacs, in the Proceedings Of Transducers '95 (1995), pages 556-559.
FIG. 1
schematically shows a prior art miniature device
10
made by using DRIE. The device comprises a substrate
20
, an oxide layer
30
overlying the substrate
20
, and a conductive layer
40
overlying the oxide layer
30
. In operation, voltage applied to the conductive layer
40
is insulated from the substrate
20
by the oxide layer
30
. Voltage breakdown may occur through the oxide layer
30
itself, but this is relatively unlikely if sufficiently thick (e.g. >1 micron) oxide layers are used. Voltage breakdown may also take place at the peripheral end
25
of the oxide layer
30
and the substrate
20
, particularly when the cross section has been damaged in a chip sawing process. Moreover, contaminating particulates generated in the sawing process and trapped in the recess area
12
may create a voltage breakdown path between the conductive layer
40
and the substrate
20
causing operation failure of the miniature device
10
. Accordingly, it is desirable to improve the device design and the process of making the device to increase maximum voltage permitted before breakdown.
In general, it is an object of the present invention to provide a miniature device having improved voltage breakdown performance.
Another object of the present invention is to provide a miniature device having an insulative layer that is partially exposed adjacent to a saw alley so that voltage breakdown due to damages of the cross section of the device caused in a sawing process is minimized.
Another object of the present invention is to provide a miniature device having an insulative layer that extends along at least a portion of the interior surface of a recess in a grounded layer so that voltage breakdown due to particulate contamination and high relative humidity on the device surfaces is prohibited.
Another object of the present invention is to provide a miniature device having an insulative layer that extends over a recess in a grounded layer so that insulative spacing between the conductive and grounded layers of the device is increased and electrical shorting between the conductive and grounded layers is inhibited.
Another object of the present invention is to provide methods of making the miniature devices having the above character.
SUMMARY OF THE INVENTION
The present invention provides a miniature device that comprises a grounded layer, an insulative layer overlying the grounded layer and a conductive layer overlying the insulative layer wherein the insulative spacing between the conductive and grounded layers is increased so as to inhibit electrical shorting between the conductive and grounded layers. In one embodiment, the insulative and grounded layers terminate at a peripheral end, and at least a portion of the insulative layer is exposed adjacent to the peripheral end to provide a relief area. In another embodiment, at least one of the grounded and conductive layers is provided with a recess, and a portion of the insulative layer extends into the recess for providing increased insulative spacing between the conductive and grounded layers. In a further embodiment, the grounded layer is provided with a recess and a portion of the insulative layer extends and overhangs the recess for providing increased insulative spacing between the conductive and grounded layers.
The present invention further provides a method of making miniature devices. The method comprises providing a substrate having a planar surface, patterning the surface of the substrate and performing an etch process to form a recess extending through the surface and defined by an interior surface, forming an insulative layer having a first portion on the planar surface of the substrate and a second portion on the interior surface of the recess, and forming a conductive layer on the first portion of the insulative layer. The step of forming an insulative layer includes thermal oxidation which comprises oxidizing the planar surface of the substrate and at least a portion of the interior surface of the recess to form an initial oxide layer, stripping the initial oxide layer, and re-oxidizing the planar surface of the substrate and the at least a portion of the interior surface of the recess to form the insulative layer.


REFERENCES:
patent: 3916434 (1975-10-01), Garboushian
patent: RE31470 (1983-12-01), Bedard et al.
patent: 5517042 (1996-05-01), Kitamura
patent: 5961849 (1999-10-01), Bostock et al.
patent: 2002/0079550 (2002-06-01), Daneman et al.
patent: 2002/0162675 (2002-11-01), Jerman et al.

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