Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-08
2004-07-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06769104
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to integrated circuits, and more particularly, to a method and apparatus for minimizing clock skew in a balanced tree when interfacing to an unbalanced load.
BACKGROUND OF THE INVENTION
Clock networks on CMOS integrated circuits have long been a source of difficulty to integrated circuit designers due to the importance of minimizing skew between clock inputs. A typical integrated circuit includes a clock tree which distributes one or more clock signals throughout the chip to clocked elements. A primary goal of a clock tree is to minimize clock skew between clocked elements. Since all clocked elements are driven from one net with a clock spine, skew is caused by differing interconnect lengths and loads. If the delay is much larger than the interconnect delays, a clock spine achieves minimum skew but with long latency. Clock skew represents a fraction of the clock period that cannot be used for computation. A clock skew of 500 ps with a 200 MHz clock means that 500 ps of every 5 ns clock cycle, or 10 percent of the performance is wasted. That is, clock skew may reduce the time allowed for certain logic paths within the design, and thus may reduce the performance of the design. Thus, for high performance designs that have strict timing requirements, it is often critical to minimize clock skew.
To minimize clock skew, typical clock trees include a number of clock drivers that are symmetrically and evenly placed on the integrated circuit die. In order to reduce clock skew in a clock tree, it is important to balance the delays through the tree carefully to minimize clock skew. There may be a number of first level drivers, which may receive a clock signal from an input buffer, and may be placed near the center of the integrated circuit. Each of the first level drivers may drive a number of second level drivers. Typically, each of the first level drivers will drive the same number of second level drivers. This is intended to maintain a matched load therebetween. The number of second level drivers may be symmetrically and evenly placed on the integrated circuit die.
A typical clock tree may include a number of levels of clock drivers. The number of clock drivers in the last level is typically sufficient to drive all of the clock loads within the design. Like all other levels, the last level of clock drivers is typically placed symmetrically and evenly throughout the integrated circuit die.
In many cases, all of the clock drivers are pre-placed on the integrated circuit die. This allows the clock drivers to be placed at any desired location on the integrated circuit die. This allows the clock tree to be evenly distributed and balanced. The routing between clock drivers may also be pre-placed and balanced.
Designing and constructing a balanced clock tree is often a time-consuming task, requiring significant design resources. Therefore, it is common for only one “worst case” clock tree to be designed. The “worst case” clock tree may then be used in each integrated circuit within a system, while still maintaining an acceptable clock skew.
After the “worst case” clock tree is designed and preplaced, the circuit designer may use a placement tool to manually place selected regions or cell of the circuit design. Thereafter, an automatic place and route tool may be used to place the remaining cells, and route the design according to the overall design specifications.
The above clock tree generating scheme has a number of limitations, some of which are described below. First, each of the clock drivers in the last level of the clock tree may have a limited drive capability, and thus may only drive a limited number of clock loads (e.g. registers, flip-flops, etc.). To use the same clock tree for multiple integrated circuit designs, and as described above, the clock tree may have to be designed to accommodate the number of clock loads in the “worst case” integrated circuit design. Because the same ‘worst case’ clock tree may be used for all integrated circuits within the system, many of the integrated circuits may be populated with more clock drivers than are actually required. This is especially limiting when the number of clock drivers that are required varies dramatically between circuit designs. These extra clock drivers may consume die area and power that could otherwise be used to implement the logical design.
FIG. 1
is a diagram illustrating a reduction in the effective clock period between registers caused by clock skew. An illustrative timing path is shown at 10, and a timing diagram therefore is shown at 30. The timing path includes a first rising edge triggered register
22
a
receiving data D
a
from a first input/output pad
20
a
, and a second rising edge triggered register
22
b
receiving data D
b
from a first input/output pad
20
a
. The first register
22
a
is clocked by a first clock signal CLK
a
and the second register
22
b
is clocked by a second clock signal CLK
b
.
With reference to the timing diagram
30
, the input clock CLK is shown at
24
. The first clock signal CLK
a
and the second clock signal CLK
b
are generated from the input clock signal CLK
24
via a clock tree or the like. The timing diagram
30
shows that the first clock signal CLK
a
is skewed relative to the second clock signal CLK
b
, as shown by t
skew
. This clock skew t
skew
may be caused by an improperly designed clock tree.
On the rising edge of the first clock signal CLK
a
, the first register
22
a
may release data Q
a
via the logic-in signal D
a
. On the rising edge of the second clock signal CLK
b
, the second register
22
b
may release data Q
b
via the logic-in signal D
a
. When the subsequent logic (not shown) is designed to receive and use the latched data Q
a
and Q
b
simultaneously, the clock skew t
skew
is clearly problematic.
Because of the clock skew t
skew
between the first and second clock signals CLK
a
and CLK
b
, the effective clock period T
eff
between the rising edge of the first clock signal CLK
a
and the subsequent rising edge of the second clock signal CLK
b
is less than the clock period T
period
, this effectively reduces the time allowed for the data to pass through subsequent logic before receiving the next incoming data, and thus may reduce the performance of the logic path.
For the above reasons, a primary goal of a clock tree is to minimize clock skew between clocked elements. As shown above, clock skew may reduce the effective clock period for certain logic paths within the design, and thus may reduce the performance of the design. For high performance designs that have strict timing requirements, clock skew may consume a substantial portion of the total clock period.
Clock skew may have a number of other detrimental effects on the performance of a circuit design, only some of which are described below. For example, clock skew may cause hold time violations when only a small amount of logic is provided between registers. Further, clock skew may cause communication problems between integrated circuits. It should be recognized that these are only illustrative examples of effects that clock skew may have on a system.
FIG. 2
is a schematic diagram illustrating a typical prior art clock tree. As indicated above, each integrated circuit typically includes a clock tree. The clock tree may distribute one or more clock signals throughout the design. As indicated above, a primary goal of a clock tree is to minimize clock skew between clocked elements.
Referring to
FIG. 2
, balanced clock trees include a number of clock drivers that are symmetrically and evenly placed on the integrated circuit die. An integrated circuit die is generally shown at
50
. There may be a number of first level drivers
55
, which may receive a clock signal from an input buffer (not shown), and may be placed near the center of the integrated circuit. Each of the first level drivers may drive a number of second level drivers
56
. Typically, each of the first level drivers
55
drives the same number of second level drivers
5
Evans Scott T.
Rodgers Richard S.
Agilent Technologie,s Inc.
Levin Naum
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