Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2000-08-23
2004-07-20
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S324000
Reexamination Certificate
active
06766460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to hardware accelerated Java execution, and more particularly to power management within a master/slave Java accelerator environment.
2. Description of the Related Art
Today's world of computer programming offers many high-level programming languages. Java, for example, has achieved widespread use in a relatively short period of time and is largely attributed with the ubiquitous success of the Internet. The popularity of Java is due, at least in part, to its platform independence, object orientation and dynamic nature. In addition, Java removes many of the tedious and error-prone tasks which must be performed by an application programmer, including memory management and cross-platform porting. In this manner, the Java programmer can better focus on design and functionality issues.
To execute a Java application a Java processor is used, which is typically realized only by software in form of a Java Virtual Machine (JVM). However, because of the problems associated with implementing a process in software, the JVM is plagued with slow performance issues.
Conventionally two techniques have been used to improve performance of Java interpretation, namely native Java execution, and partial hardware interpretation of Java instructions. The native Java execution approach uses hardware to build a real Java processor. However, this technique presents a severe flaw in that it removes the Java concept of the ‘outside machine,’ and therefore eliminates a large amount of software, which is not capable of executing on such a Java processor.
The partial hardware interpretation of Java instructions approach uses hardware assist to improve the interpretive process. This configuration is often called a Java accelerator. Essentially, it approximates the performance of an assembly language interpreter executing out of zero wait state memory.
One implementation of the Java accelerator uses a master/slave configuration wherein the master (host) processor executes all instructions other than Java instructions, and the slave processor executes exclusively Java instructions. However, conventional systems using this approach have been fraught with problems associated with power management between the host and the slave processors. This problem is exasperated when both processors are implemented on small, battery powered, mobile devices, where power conservation is very important.
Historically, problems associated with the power management of computing devices resulted from attempts to detect when a system, or various component parts within a system, is performing meaningful work. Often, conventional power management systems monitor input and output (I/O) signals in conjunction with idle timers to detect when power to devices can be shut off.
In other conventional power management systems, the frequency of the processor interface is varied, thereby lowering the power consumption of the computer system. Still other conventional power management systems use a method called clock throttling to lower the power consumption of the microprocessor and hence the power consumption of the computer system. Under this method, when a microprocessor is deemed not to be doing meaningful work, an input to the microprocessor is changed which effectively tells the microprocessor to stop using its clock internally. By changing the input to the microprocessor, the microprocessor is slowly throttled back so that the microprocessor will not burn as much energy thereby reducing the power consumption of the computer system. Although recent prior art power management decision processes have been improved by making them operating system (OS) centric, most conventional power management decisions are only guesses.
While the above methods may result in a reduction of power consumption, none of the methods are combined with a reduction in the operating voltages of each processor in the system, which would further reduce power consumption in the system. Controlling both the operating voltages and operating frequencies of both the host and Java processor would allow for optimal power and performance tradeoffs in the computer system.
In view of the forgoing, there is a need for systems and methods that provide improved power management within a Java accelerator. The power management systems should control both the operating voltages and operating frequencies of the host and Java processor. Moreover, the power management system should ensure that neither the power supply nor the digital circuitry is stressed during operating condition changes, and should ensure adequate time is available between operating condition changes to allow for memory updates between processors.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing an improved power management system for a Java accelerator. The power management system of the present invention controls both the operating voltages and operating frequencies of the host and Java processor, thus allowing for optimal power and performance in the computer system. In one embodiment, a power management method which provides power management for a hardware based Java accelerator is disclosed. Initially, a Java mode signal is provided from a host processor in response to initiating a Java application. Thereafter, power to the host processor is reduced, and power to a Java processor is increased in response to the Java mode signal. Then, when execution of the Java application halts, a Java completion signal is generated from the Java processor, thus signaling the system to return control back to the host processor.
In another embodiment, a power management system which provides power management for a hardware based Java accelerator is disclosed. The power management system includes a host processor coupled to power generation circuitry. The host processor includes a Java mode signal port capable of providing a Java mode signal. Further included in the power management system is a Java processor, which is also coupled to the power generation circuitry. The Java processor includes a Java completion signal port, which is capable of providing the Java completion signal. In use, the power generator circuitry reduces power to the host processor, and increases power to the Java processor in response to receiving the Java mode signal. Further, in response to receiving the Java completion signal, the power generator circuitry increases power to the host processor and reduces power to the Java processor.
A ramp circuit method for dampening changes provided to a processor is disclosed in yet a further embodiment of the present invention. The ramp circuit method begins by obtaining a target value that represents a desired frequency or voltage that the processor is to be set at. Then, the target value is compared to a current value to obtain a difference value. Similar to target value, the current value is a current frequency or voltage that the processor is currently operating at. The current value is then adjusted when the difference value is outside a predefined threshold value, which can be a range of values, or a single value, such as zero. The above operations are then repeated until the difference value is within the predefined threshold value.
Advantageously, the present invention allows for optimal power and performance in the computer system by controlling both the operating frequencies and operating voltages of the host and Java processor. Furthermore, when both the frequency and voltage are controlled, the voltage is increased prior to increasing the frequency, and the frequency is decreased prior to decreasing the voltage. This assures that the system does not run at a frequency that is too fast for the current voltage, thus resulting in further power savings.
Finally, it will become apparent to those skilled in the art that the power management system of the present invention ensures adequate time is available between operating condition changes to allow for memory updates bet
Evoy David R.
Goff Lonnie C.
Sexton Bonnie
Du Thuan
Lee Thomas
Ure Michael J.
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