Use of atomic oxygen process for improved barrier layer

Details Use of atomic oxygen process for improved barrier layer Use of atomic oxygen process for improved barrier layer

2002-10-23

2004-09-14

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000

Reexamination Certificate

active

06791138

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices and, in particular, to a method of increasing the performance of such devices.
BACKGROUND OF THE INVENTION
The integration of a large number of components on a single IC chip requires complex interconnects. Ideally, the interconnect structures should be fabricated with minimal signal delay and optimal packing density. Because of their increasing importance, the qualities of the interconnect structures drastically affect the reliability and performance of fabricated integrated circuits. Currently, the reliability of electrical contacts are increasingly defining the limits in performance and density of modern very-large scale integrated (VLSI) circuits.
A conventional pair of transistors for integrated memory cells is illustrated in FIG.
1
. Respective access transistors
33
are formed within a well
13
of a semiconductor substrate
12
. The well and transistors are surrounded by a field oxide region
14
that provides isolation. The pair of access transistors have respective gate stacks
30
, which include an oxide layer
18
, a conductive layer
20
, such as polysilicon, and a nitride cap
22
.
Insulating spacers such as the nitride spacers
32
of
FIG. 1
are typically formed on sidewalls of the gate stacks
30
to provide electrical insulation of the gate stacks
30
and source/drain regions
40
. The nitride spacers
32
are also employed in the formation of lightly doped drain (LLD) regions
42
(
FIG. 1
) between the source/drain regions
40
in the semiconductor substrate
12
and the channel region beneath the gate stacks
30
. As known in the art, source/drain regions
40
are formed by doping the semiconductor substrate
12
after formation of the nitride spacers
32
with the same type of dopant used to form the LLD regions
42
, but with a heavier dosage (either P+ or N+).
After formation of the source/drain regions
40
, a polysilicon plug
21
(
FIG. 2
) is typically formed in a contact opening of an insulating layer
24
(FIG.
2
), to directly connect to a source or drain region
40
of the semiconductor device. For simplicity,
FIG. 2
illustrates only a partial middle view of the structure of FIG.
1
. The insulating layer
24
(
FIG. 2
) could be, for example, borophosphosilicate glass (BPSG), borosilicate glass (BSG), or phosphosilicate glass (PSG). Once the polysilicon plug
21
is formed, the whole structure, including the substrate
12
with the gate stacks
30
, is chemically or mechanically polished to provide a planarized surface. As known in the art, additional contact openings or vias are formed over the polysilicon plug so that a metal layer bit line or metal electrode of a capacitor plate, for example, may then be deposited and patterned to contact with the polysilicon plug.
The insulating layer
24
(
FIG. 2
) is typically composed of a borophosphosilicate glass (BPSG) or a non-doped silicate glass (NSG), which is formed over the gate stacks
30
and the source/drain regions
40
by deposition, for example, and then undergoes a thermal treatment to facilitate the planarizing of the insulating material. Since the thermal treatment of the insulating layer
24
typically requires temperatures higher than 500° C., boron (B) and/or phosphorous (P) atoms from the BPSG insulating layer
24
migrate into the adjacent source/drain regions
40
and under the nitride spacers
32
in the LDD regions
42
during these high-temperature steps. Although the boron/phosphorous migration into the source/drain regions
40
occurs in limited regions, near or at a source/drain-BPSG interface
51
(FIG.
2
), this interface is degraded and the performance of the device affected. A major drawback posed by the migration of impurity boron/phosphorous atoms at the source/drain-BPSG interface
51
is the decrease in the “refresh time” of the DRAM device, and consequently an increase in the DRAM error rate. The “refresh time” of a DRAM cell is defined as the length of time over which the DRAM cell can retain a sufficient amount of charge for its intended data state to be determined by a sense amplifier circuit. Before this period of time expires, the DRAM cell must be reprogrammed or “refreshed” and, consequently, it is desirable that the refresh time between the refresh operations be as along as possible.
Barrier layers have been introduced in an attempt to minimize the boron/phosphorous diffusion at the source/drain-BPSG interface
51
(FIG.
2
). For example, a composite barrier layer
52
(
FIG. 3
) comprising a tetraethylorthosilicate TEOS liner
52
a
and a nitride liner
52
b
is illustrated in FIG.
3
. While the composite barrier layer
52
suppresses the diffusion of the boron/phosphorous impurity atoms at the source/drain-BPSG interface
51
, there is a problem in that the deposition of the TEOS liner
52
a
is highly non-conformal. In addition, the formation of the TEOS liner
52
a
typically employs a TEOS precursor gas; however, this TEOS precursor gas is not pure and contains many impurity atoms, for example carbon (C) impurities, which further diffuse into the active regions
40
,
42
. Nitride liners, such as a silicon nitride (Si
3
N
4
) barrier layer, disposed directly over the source/drain regions
40
also pose problems in that the mobility of the silicon (Si) atoms in the semiconductor substrate
12
is greatly degraded as a result of the Si
3
N
4
/Si interface, which as known in the art, increases the electrical resistance in the electrical connection region.
Accordingly, there is a need for an improved method for preventing the migration of impurity atoms into the active regions of a DRAM device, as well as a method for increasing the refresh time and reducing the error rate of such DRAM devices. There is also a need for a novel barrier layer that would prevent the occurrence of the above-mentioned problems.
BRIEF SUMMARY OF THE INVENTION
The present invention provides a composite barrier layer formed between a glass insulating layer and active regions of a memory device, for example a DRAM device, to eliminate the diffusion of impurity atoms from the glass insulating layer into the active regions of the device.
The composite barrier layer comprises an oxide layer formed by atomic deposition process and an insulating layer, for example a nitride barrier layer, formed over the oxide layer.
These and other features and advantages of the invention will be more apparent from the following detailed description which is provided in connection with the accompanying drawings, which illustrate exemplary embodiments of the invention.


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