Graphics engine command FIFO for programming multiple...

Details Graphics engine command FIFO for programming multiple... Graphics engine command FIFO for programming multiple...

2003-01-20

2004-05-25

Tung, Kee M. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphics display memory system

First in first out

C345S559000

Reexamination Certificate

active

06741257

ABSTRACT:

BACKGROUND OF INVENTION
This invention relates to graphics systems, and more particularly to addressing of programmable registers.
Personal computers (PCs) and other computer systems have a variety of controller integrated circuits (ICs) or chips that control subsystems such as for graphics, disks, and general system logic. Such controller chips are usually programmable. For example, the graphics controller can be programmed with the display resolution, such as the number of pixels in a horizontal line, or the number of lines on a screen. Memory-controller chips can be programmed with numbers of clock cycles for memory accesses, so that the timing signals generated by the controller chip can be adjusted for faster memory chips or faster bus clocks.
Advanced graphics systems often employ specialized engines, such as a bit-block-transfer BitBlt engine. Graphics data and commands can be written to a command first-in-first-out (FIFO) by a host processor, allowing the BitBlt engine to read and process graphics data and commands at its own pace.
The host microprocessor's address space is typically partitioned into memory and input/output (I/O) address spaces. While a large memory address space such as 4 GigaBytes (32 address bits) is provided, the I/O address space is typically much smaller, perhaps only 64 Kbytes (16 address bits). I/O addresses are used for accessing peripheral devices such as I/O ports, disk drives, modems, mouse and keyboard, and the controller chips. Often certain ranges of I/O addresses are reserved for certain types of peripherals, such as graphics, disks, and parallel ports. Thus the number of I/O addresses available to a peripheral controller chips is often limited.
Some of the programmable registers may be assigned addresses in the memory space rather than the I/O space. Since memory accesses are often faster than I/O accesses, memory-mapped registers can be accessed more quickly, improving performance. Frequently-accessed registers are often memory-mapped rather than I/O.
Programmable Registers
FIGS. 1
,
2
FIG. 1
shows a computer system with a controller chip with programmable registers. A central processing unit (CPU)
12
is a microprocessor that executes instructions in a program stored in memory
14
or in a BIOS ROM (not shown). Display
16
is controlled by graphics controller
10
. Programs executing on CPU
12
can update the information shown on display
16
by writing to a frame buffer inside or controlled by graphics controller
10
. Graphics controller
10
reads lines of pixels from the frame buffer and transfers them to display
16
, which can be a cathode-ray tube (CRT) monitor or a flat-panel display.
Bus
11
connects CPU
12
and graphics controller
10
, and includes an address bus and a data bus. Bus
11
may be divided into separate sections by buffer chips. Often a high-speed bus such as a PCI (Peripheral Component Interconnect) or AGP (Accelerated Graphics Port) bus is used to connect to graphics controller
10
.
Graphics controller
10
includes programmable registers
20
that control various features. For example, power-saving modes, display characteristics, timing, and shading can be controlled by CPU
12
writing to programmable registers
20
. Registers are frequently written during 3D rendering or bitblt operations.
FIG. 2
highlights an address decoder that selects a data register for access. A shared address/data bus is used where the address is output during a first bus cycle while the data is output during a second bus cycle. During a first bus cycle, the CPU outputs an address on the bus to decoder
31
. This address is decoded by decoder
31
, causing selector
34
to selects one of the registers in programmable register
20
for access. The other programmable registers are deselected and cannot be accessed until a new address is written to decoder
31
.
In the second bus cycle, the CPU writes a data value to the bus. The data written by the CPU is written through selector
34
to the register in programmable registers
20
that was selected by the address in decoder
31
. The CPU may also read the selected register rather than write the selected register since selector
34
provides a bi-directional data path, depending on the read/write control signal from the CPU. For the PCI bus, address decoding takes 1, 2, or 3 clock cycles and data is written on the fourth clock cycle. A two-cycle idle time is necessary. Thus each PCI bus transaction requires 6 clock cycles.
The values written to programmable registers
20
are used to control features of the controller chip. For example, programmable registers
20
can output a number of pixels per horizontal line, and a number of lines in a screen, to counters
38
in a graphics controller. When the number of pixels written to the display matches the value of pixels/line from programmable registers
20
, then a horizontal sync HSYNC pulse is generated. When the number of lines counted matches the total number of lines from programmable registers
20
, then the vertical sync VSYNC is generated. Controls for windows within a screen can likewise come from programmable registers
20
, such as for a movie window as described in Transparent Blocking of CRT Refresh Fetches During Video Overlay Using Dummy Fetches, U.S. Pat. No. 5,754,170 by Ranganathan et al., and assigned to NeoMagic Corp.
FIG. 3
shows standard bus cycles to program registers. During the first bus cycle, a first address A
1
is output on the bus from the CPU to the controller chip. Address A
1
is the address of a first programmable register. In the second bus cycle, data D
1
is output on the bus from the CPU to the controller chip. The controller chip stores data D
1
from the bus into the programmable register for address A
1
.
A second data value is written to a second programmable register during the third and fourth bus cycles. Address A
2
is output during the third bus cycle while data D
2
is output during the fourth bus cycle. The controller chip writes data D
2
to the register identified by address A
2
. A third data value is written to another programmable register in the fifth and sixth bus cycles. Data D
5
is written to the controller chip's register for address A
5
.
Each programmable register written requires a 2-bus-cycle access where the address is followed by the data. The programmable registers can be written in any order, but the correct address must precede the data value in each pair of bus cycles. Data may be read rather than written to the programmable registers by not asserting a write signal from the CPU.
Burst Access
FIGS. 4
,
5
High-speed busses often support higher data bandwidth using a burst access, ring a burst-access cycle, the address input in the first bus cycle is followed by several data values input over several bus cycles. A predefined burst order is used to determine the addresses of the data values in the burst sequence.
FIG. 4
is a diagram of data being bursted into programmable registers. Burst decoder
33
receives a starting address A
1
during a first bus cycle. Selector
34
routes the data to the A
1
data register in programmable registers
20
having the starting address (A
1
) in the second bus cycle.
During the next 3 bus cycles, data values are received without addresses. The addresses of these three data values are implied by the burst rules. The burst rules define the address order during burst cycles. For purely sequential burst rules, the implied addresses of the next 3 data values are A
1
+1, A
1
+2, and A
1
+3. Often the burst addresses are interleaved so the addresses are somewhat mixed in order: A
1
+2, A
1
+1, then A
1
+3. The burst order is usually a fixed order defined by the architecture. Although a purely sequential burst is used as the example, other semi-sequential or interleaved burst orders may be substituted. The burst sequence is usually for sequential addresses (
1
,
2
,
3
,
4
), or semi-sequential addresses (
1
,
3
,
2
,
4
, or
1
,
4
,
2
,
3
, or others) in some predefined sequence.
During the

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